OXMPCI952 Datasheet, PDF (29/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
OXmPCI952
5.4 Accessing Local configuration registers
The local configuration registers are a set of device specific registers which can be accessed from either function. The local
configuration registers exist behind BAR4 and BAR5 for function 0, and behind BAR2 and BAR3 for function 1. For I/O
transactions, access is limited to byte reads/writes. For Memory Transactions, accesses can be Word or Dword accesses,
however on little-endian systems such as Intel 80x86 the byte order will be reversed.
The following table lists the definitions of the local registers, with the offsets (from the Base Address Register) defined for each
local register.
5.4.1 Local Configuration and Control register ‘LCC’ (Offset 0x00)
This register defines control of ancillary functions such as Power Management, external clock reference signals and the serial
EEPROM. The individual bits are described below.
Bits Description
Read/Write
EEPROM _PCI
0
Mode Status. This bit returns the state of the Mode pin.
-
R
1
Reserved.
-
R
2
Enable UART clock output. When this bit is set, a buffered version of
W
RW
the UART clock is output on the pin “UART_Clk_Out”. When this bit is
low, the UART_Clk_Out is permanently low.
4:3
Endian Byte-Lane Select for memory access to 8-bit peripherals.
W
RW
00 = Select Data[7:0]
10 = Select Data[23:16]
01 = Select Data[15:8]
11 = Select Data[31:24]
Memory access to OXmPCI952 is always DWORD aligned. When
accessing 8-bit regions like the internal UARTs, the 8-bit Local Bus and
the parallel port, this option selects the active byte lane. As both PCI and
PC architectures are little endian, the default value will be used by
systems, however, some non-PC architectures may need to select the
byte lane.
6:5
Power-down filter time. These bits define a value of an internal filter
W
RW
time for a power-down interrupt request in power management circuitry
in Function0. Once Function0 is ready to go into power down mode,
OXmPCI952 will wait for the specified filter time and if Function0 is still in
power-down request mode, it can assert a PCI interrupt (see section
5.6).
00 = power-down request disabled
10 = 129 seconds
01 = 4 seconds
11 = 518 seconds
7
Function1 MIO2_PME Enable. A value of ‘1’ enables MIO2 pin to set
W
RW
the PME_Status in PMCSR register, and hence assert the PME# pin if
enabled. A value of ‘0’ disables MIO2 from setting the PME_Status bit
(see section 5.6).
23:8 Reserved. These bits are used for test purposes. The device driver must
-
R
write zeros to these bits.
24
EEPROM Clock. For PCI read or write to the EEPROM, toggle this bit to
-
W
generate an EEPROM clock (EE_CK pin).
25
EEPROM Chip Select. When 1 the EEPROM chip-select pin EE_CS is
-
W
activated (high). When 0 EE_CS is de-active (low).
26
EEPROM Data Out. For writes to the EEPROM, this output bit is the
-
W
input-data for the EEPROM. This bit is output on EE_DO and clocked
into the EEPROM by EE_CK.
27
EEPROM Data In. For reads from the EEPROM, this input bit is the
-
R
output-data of the EEPROM connected to EE_DI pin.
28
EEPROM Valid. A 1 indicates that a valid EEPROM program is present
-
R
Reset
X
0
0
00
00
0
0000h
0
0
0
X
X
DS-0020 Jun 05
Page 29