OXMPCI952 Datasheet, PDF (31/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
OXmPCI952
Bits
11:10
13:12
15:14
17:16
19:18
21:20
Bit 23:22
Bit 25:24
Bit 26
Description
MIO5 Configuration Register.
00 -> MIO5 is a non-inverting input pin
01 -> MIO5 is an inverting input pin
10 -> MIO5 is an output pin driving ‘0’
11 -> MIO5 is an output pin driving ‘1’
MIO6 Configuration Register.
00 -> MIO6 is a non-inverting input pin
01 -> MIO6 is an inverting input pin
10 -> MIO6 is an output pin driving ‘0’
11 -> MIO6 is an output pin driving ‘1’
MIO7 Configuration Register.
00 -> MIO7 is a non-inverting input pin
01 -> MIO7 is an inverting input pin
10 -> MIO7 is an output pin driving ‘0’
11 -> MIO7 is an output pin driving ‘1’
MIO8 Configuration Register.
00 -> MIO8 is a non-inverting input pin
01 -> MIO8 is an inverting input pin
10 -> MIO8 is an output pin driving ‘0’
11 -> MIO8 is an output pin driving ‘1’
MIO9 Configuration Register.
00 -> MIO9 is a non-inverting input pin
01 -> MIO9 is an inverting input pin
10 -> MIO9 is an output pin driving ‘0’
11 -> MIO9 is an output pin driving ‘1’
MIO10 Configuration Register.
00 -> MIO10 is a non-inverting input pin
01 -> MIO10 is an inverting input pin
10 -> MIO10 is an output pin driving ‘0’
11 -> MIO10 is an output pin driving ‘1’
Reserved. The device driver must write zeros to these bits.
Reserved. The device driver must write zeros to these bits.
Reserved. Any PCI write transactions must not affect the status of this bit.
Read/Write
EEPROM _PCI
W
RW
W
RW
W
RW
W
RW
W
RW
W
RW
W
R/W
W
R/W
W
R/W
Bit 27
Bit 28
Bit 29
Bit 30
MiniPCI Mode Status
When set, indicates that the device is operating in the miniPCI mode.
When clear, device is operating in the PCI mode.
Reserved
Clock Control Handling via Power Management
When set (1), the clock control circuitry handling the CLKRUN# line is
controlled by the power management states of function 0 and function 1.
This bit is only relevant for the miniPCI mode of operation.
Disable Clock Control Circuitry (CLKRUN#)
When set (1), the clock control circuitry handling the CLKRUN# line is
disabled, allowing the host to stop the PCI_CLK at the next available
opportunity. Circuitry Is enabled by default to prevent clock stopping.
This bit is only relevant for the miniPCI mode of operation.
-
R
-
R
W
R/W
W
R/W
Reset
00
00
00
00
00
00
00
0
1
(following
use of
eeprom)
X
1
0
0
DS-0020 Jun 05
Page 31