OXMPCI952 Datasheet, PDF (102/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
OXmPCI952
2 Consecutive Write Transactions to ECP DFIFO
PCI CLK no
1
6
9-10
10
11
14-15
17
- Start of 1^st PCI write to ECP DFIFO register
- Start of 1^st ECP forward Transfer Cycle
- 1^st PCI transaction terminates with a “Data Transfer”
- Peripheral Asserts BUSY in response to the host driving STB_N low
- Start of 2^nd PCI write to ECP DFIFO register. Current ECP forward transfer remains unaffected.
- Host responds to BUSY by de-asserting STB_N (2 clock cycles after sampling BUSY) – 1^st ECP forward transfer.
- Peripheral Deasserts BUSY
- End of 1^st ECP forward transfer (2 clock cycles after sampling BUSY)
18
Start of 2nd ECP forward Transfer Cycle
Tstb (PCI clk to valid STB_N)
- 22ns max*
Tpd (PCI clk to valid port Address) - 22ns max*
ECP Forward Transfer Cycle duration is dependant upon the timing response of the peripheral’s BUSY line and the parallel port
filters. Example waveform has the parallel port filters disabled. An extra 2 PCI CLK cycles will be incurred in the response of the
host to the peripheral’s BUSY line when the filters are enabled.
* These values are applicable to a pin loading of100pF.
DS-0020 Jun 05
Page 102