OXMPCI952 Datasheet, PDF(37/108 Page) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

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OXMPCI952 Datasheet, PDF (37/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

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OXFORD SEMICONDUCTOR LTD.

OXmPCI952

Bits Description

Read/Write

30:22 MIO Interrupt Mask. When set (=1) these bits enable each MIO[10:2] pin to

assert a PCI interrupt respectively. When cleared (=0) they prevent the

respective pins from asserting a PCI interrupt.2

31 Reserved.

Reset

1FFh

Note 1:

Note 2:

Note 3:

GIS[3:0] are the inverse of UIS[18], UIS[12], UIS[6] and UIS[0] respectively. Systems that do not require the Local Bus or parallel port need not read

this register to identify the source of the interrupt as long as they read the UIS (offset 18h) register.

The returned value is either the direct state of the corresponding MIO pin or its inverse as configured by the Multi-purpose I/O Configuration register

âMICâ (offset 0x04). As the internal MIO can assert a PCI interrupt, the inversion feature can define each external interrupt to be defined as active-low

or active-high, as controlled by the MIC register.

When the MIO[0] pin has been set-up as an input or output, this can be made to generate an interrupt when the MIO[0] Interrupt Mask (bit 20) is set

(=1). This bit enables MIO[0] pin to assert a PCI interrupt.

When the MIO[1] pin has been set-up as an input or output, this can be made to generate an interrupt when the MIO[1] Interrupt Mask (bit 21) is set

(=1). This bit enables MIO[1] pin to assert a PCI interrupt.

The UART Interrupt Mask register bits are all set after a hardware reset to enable the interrupt from both the internal UARTs. This will cater for

generic device-driver software that does not access the Local Configuration Registers. The default setting for UART Interrupt Mask bits can be

changed using the serial EEPROM. Note that even though by default the UART interrupts are enabled in this register, since after a reset the IER

registers of individual UARTs disables all interrupts, a PCI interrupt will not be asserted after a hardware reset.

DS-0020 Jun 05

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