OXMPCI952 Datasheet, PDF (42/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
OXmPCI952
5.7 MiniPCI Support
The OXmPCI952 device operates in the miniPCI mode
when Pin 88 (PCI/miniPCI Selection pin) is tied HIGH.
Otherwise, the device operates in the PCI mode.
In the miniPCI mode, the following changes take place to
the device functionality and pin definitions.
Function/Pin
Z_INTA
Z_INTB
D3cold Support
MiniPCI mode
PCI interrupt pin
For both function 0 and function 1.
Redefined as a CLKRUN# pin
No PCI interrupts available on this pin
PME# from D3 Cold supported
Available and indicated in the PCI
Power Management Registers
PCI Mode
PCI Interrupt pin.
For both function 0 and function 1.
Optional PCI interrupt pin
Unused by default.
No PME# D3 cold supported.
As indicated in the PCI Power
Management Registers.
CLKRUN#
The OXmPCI952 device is not tolerant to clock stopping on
the PCI_CLK line, for full UART functionality. While the two
UARTs themselves are not dependent upon the PCI_CLK
line, and use the crystal oscillator pin as their main clock
source, some parts of the device require that the PCI_CLK
be operational (ie not stopped) to allow reliable operation of
the internal UARTs. Such parts include writing/reading of
the UART registers and interrupt handling. For this reason,
the OXmPCI952 device implements CLKRUN# to prevent
the host from stopping the PCI_CLK (until such time it is
not needed). The circuitry handling the CLKRUN# line is
compliant to the CLKRUN# requirements as defined by the
PCI Mobile Design Guide, version 1.1.
Provided that the Central Resource holds the CLKRUN#
line active (low), to indicate that the PCI_CLK is enabled,
then there is no intervention by the OXmPCI952 device
which keeps it’s side of the CLKRUN# driver inactive. The
CLKRUN# line is a bi-directional pin. When the Central
Resource synchronously de-asserts the CLKRUN# line (by
initially driven the line high and then leaving it in the high
impedance state) to signal the Central Resource’s intention
to stop (or slow) the PCI_CLK, then it is prevented from
doing so by the target that asserts (drives low) the
CLKRUN# line 2 clock cycles following the de-assertion.
The CLKRUN# line is only asserted by the target for 2
clock cycles, during which time the Central Resource is
expected to drive (and hold) the CLKRUN# line asserted,
until the next attempt by the host to stop the clock. In this
case, the cycle repeats.
By default, the clock control circuitry of the OXmPCI952 (in
the miniPCI mode) is always enabled. This means that the
Central Resource is prevented from stopping the PCI_CLK
DS-0020 Jun 05
at all times, as all requests by the Central Resource to stop
this clock (by de-asserting the CLKRUN# line) are met by
the target re-asserting the CLKRUN# line 2-clock cycles
later. This may be an issue from a power management
point of view as this default behaviour may prevent the
system from going into a low power state or may result in
the system being partially shut-down due to the need to
maintain PCI_CLKs to the OXmPCI952 based miniPCI
card. The clock control circuitry associated with the
CLKRUN# line has been provided with controls to help
overcome this.
In the miniPCI mode, the local registers provide 2 controls
associated with the CLKRUN# line. These Read-Write
fields are accessible via PCI transactions or can be set up
by the external EEPROM by downloading into the MIC
register of the Local Register Zone.
Control
CLKRUN# Circuitry Disable
CLKRUN# Control via
Power Management
MIC
Register
Bit
Bit 30
Bit 29
Default
State
0
0
Page 42