OXMPCI952 Datasheet, PDF (43/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
Bits
30:29
00
01
10
11
CLKRUN Circuitry Status
CLKRUN#’ Operation Enabled
(Never Stop PCI-CLK)
CLKRUN# Operation via Power
Management Control
CLKRUN# Operation Disabled
(Allow PCI_CLK to stop)
CLKRUN# Operation Disabled
(Allow PCI_CLK to stop)
The Clkrun# Circuitry Disable bit, allows the device drivers
to disable (and re-enable) the clock control circuitry
associated with the CLKRUN# line to meet the overall
Power Management of the device and the system. When
the CLKRUN# circuitry is disabled, then when the
CLKRUN# line is deasserted by the Central Resource at
the next available opportunity, no attempt is made by the
target to assert the CLKRUN# line thereby allowing the
Central Resource to stop the PCI_CLK. Once the PCI_CLK
is stopped, it is still possible to re-enable the clock run
circuitry by writing to the disable field (with a ‘0’) as the
Central Resource is expected to restart the PCI_CLK for a
sufficient time to allow the write transaction to take place.
Once the transaction has been completed, the clock control
circuitry will then prevent the central resource from
stopping the PCI_CLK until the clock control circuitry is
again disabled. While it is perfectly feasible that the clock
control circuitry can be disabled (re-enabled) at leisure, the
clock control circuitry should only be disabled prior to the
device being placed into the low power states D2/D3 by the
host, when no operations other than a wake-up are
expected from the UARTs. Some interaction between
device drivers and the host will be required to determine
OXmPCI952
the most suitable point to disable the clock control circuitry.
Disabling the clock control circuitry when the OXmPCI952
device is in the fully operational state (eg D0 state) is not
recommended as some hosts have been designed to
periodically attempt to stop the PCI_CLK as a normal
routine. In these cases, if the clock control circuitry has
been disabled then the PCI_CLK will be stopped at the
next opportunity. If large file transfers are/will be taking
place when this event has occurred then this may lead to
corrupted data being transmitted/received.
In addition to the Clkrun# Circuitry Disable bit, there is an
additional control called Clkrun# Control via Power
Management. As the name suggests, this allows the clock
control logic associated with the CLKRUN# line to be
controlled by the Power Management states of the
OXmPCI952 device. This is a hardware assist and does
not require software involvement with the exception of
enabling this field in the 1^st place (although this can also be
achived via the external eeprom).
When the Clkrun Control via Power Management is
selected, the device makes use of the knowledge that any
attempts by the host (Central Resource) to place both of
the functions into a low power state (states D2 or D3 in
power management terminology) is a pre-empt condition to
the host stopping the PCI-CLK to the OXmPCI952 device
in order to reduce power consumption of the card and thus
the system. The host is not expected to stop the PCI-CLK
to the OXmPCI952 device when at least 1 of the 2
functions is in the fully operation state (D0 state). A state-
machine has been built-in that handles the clock control
circuitry according to the D0, D2, D3 states of each
function. This is as shown overleaf.
DS-0020 Jun 05
Page 43