OXMPCI952 Datasheet, PDF (86/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
OXmPCI952
11 AC ELECTRICAL CHARACTERISTICS
11.1 PCI Bus
The timings for PCI pins comply with PCI Specification for the 3.3 Volt signalling environment.
AC Specifications
Symbol Parameter
Condition
Min
Max
Unit Note
Ioh(AC) Switching Current High
0<Vout<=0.3Vcc
-12Vcc
mA
1
0.3Vcc<Vout<0.9Vcc -17.1(Vcc-Vout)
mA
1
0.7Vcc<Vout<Vcc
Equation C mA 1,2
Iol(AC) Switching Current Low
Vcc>Vout>=0.6Vcc
16Vcc
mA
1
0.6Vcc>Vout>0.1Vcc
26.7Vout
mA
1
0.18Vcc>Vout>0
Equation D mA 1,2
Slewr
Output Rise Slew Rate
0.2Vcc-0.6Vcc load
1
4
V/ns 3
Slewf
Output Fall Slew Rate
0.6Vxx-0.2Vcc load
1
4
V/ns 3
1. This specification does not apply to PCI_CLK and RESET# pins. “Switching Current High” specifications are not relevant to
SERR#, PME#, INTA#, INTB#.
2.
Equation C
Ioh = (98.0/Vcc)*(Vout-Vcc)*(Vout+0.4Vcc) for Vcc>Vout>0.7Vcc
Equation D
Iol = (256/Vcc)*Vout*(Vcc-Vout)
for 0v<Vout<0.18Vcc.
3. For Test Circuit See Section 4.2.2.2 of PCI Local Bus Specification. This figure does not apply to Open-Drain Outputs.
11.2 Local Bus
By default, the Local bus control signals change state in the cycle immediately following the reference cycle, with offsets to
provide setup and hold times for common peripherals in Intel mode. The tables below show the local bus parameters using
default values for LT1/LT2 local registers. However each of these can be increased or decreased by a number of PCI clock
cycles by adjusting the parameters in registers LT1 and LT2.
All timing parameters assume a loading of 100pF on the local bus output pins.
Symbol
tref
tza
tard
tzrcs1
tzrcs2
tcsrd
trdcs
tzrd1
tzrd2
tdrd
tzd1
tzd2
tsd
thd
Parameter
IRDY# falling to reference LBCLK
Reference LBCLK to Address Valid
Address Valid to LBRD# falling
Reference LBCLK to LBCS# falling
Reference LBCLK to LBCS# rising
LBCS# falling to LBRD# falling
LBRD# rising to LBCS# rising
Reference LBCLK to LBRD# falling
Reference LBCLK to LBRD# rising
Data bus floating to LBRD# falling
Reference LBCLK to data bus floating at the start of the
read transaction
Reference LBCLK to data bus driven by OXmPCI952 at the
end of the read transaction
Data bus valid to LBRD# rising
Data bus valid after LBRD# rising
Min
Max
Nominally 2 PCI clock cycles
3.8
12.0
2.8
9.6
3.2
11.0
3 PCI clks + 6.6 3 PCI clks + 21.6
3.2
10.6
3.0
10.0
6.6
21.6
3 PCI clks + 3.6 3 PCI clks + 11.6
2.6
8.2
4.0
13.4
4 PCI clks + 3.8 4 PCI clks + 13.0
11.4
-
0
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 27: Read operation from Intel-type Local Bus
DS-0020 Jun 05
Page 86