OXMPCI952 Datasheet, PDF (32/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
OXmPCI952
Bits
Bit 31
Description
Parallel Port Filter Disable
When set (1) disables the noise filters on the parallel port data lines and
status lines. Filters are enabled by default.
This bit is only relevant for the parallel port.
Read/Write
EEPROM _PCI
W
R/W
Reset
0
5.4.3 Local Bus Timing Parameter register 1 ‘LT1’ (Offset 0x08):
The Local Bus Timing Parameter registers (LT1 and LT2) define the operation and timing parameters used by the Local Bus.
The timing parameters are programmed in 4-bit registers to define the assertion/de-assertion of the Local Bus control signals.
The value programmed in these registers defines the number of PCI clock cycles after a Reference Cycle when the events
occur, where the reference Cycle is defined as two clock cycles after the master asserts the IRDY# signal. The following
arrangement provides a flexible approach for users to define the desired bus timing of their peripheral devices. The timings refer
to I/O or Memory mapped access to BAR0 and BAR1 of Function1.
Bits
3:0
7:4
11:8
15:12
19:16
23:20
Description
Read Chip-select Assertion (Intel-type interface). Defines the number
of clock cycles after the Reference Cycle when the LBCS[3:0]# pins are
asserted (low) during a read operation from the Local Bus.¹
These bits are unused in Motorola-type interface.
Read Chip-select De-assertion (Intel-type interface). Defines the
number of clock cycles after the Reference Cycle when the LBCS[3:0]#
pins are de-asserted (high) during a read from the Local Bus. ¹
These bits are unused in Motorola-type interface.
Write Chip-select Assertion (Intel-type interface). Defines the number
of clock cycles after the Reference Cycle when the LBCS[3:0]# pins are
asserted (low) during a write operation to the Local Bus. ¹
These bits are unused in Motorola-type interface.
Write Chip-select De-assertion (Intel-type interface). Defines the
number of clock cycles after the reference cycle when the LBCS[3:0]#
pins are de-asserted (high) during a write operation to the Local Bus. ¹
Read-not-Write De-assertion during write cycles (Motorola-type
interface). Defines the number of clock cycles after the reference cycle
when the LBRDWR# pin is de-asserted (high) during a write to the Local
Bus. ¹
Read Control Assertion (Intel-type interface). Defines the number of
clock cycles after the Reference Cycle when the LBRD# pin is asserted
(low) during a read from the Local Bus. ¹
Read Data-strobe Assertion (Motorola-type interface). Defines the
number of clock cycles after the Reference Cycle when the LBDS[3:0]#
pins are asserted (low) during a read from the Local Bus. ¹
Read Control De-assertion (Intel-type interface). Defines the number of
clock cycles after the Reference Cycle when the LBRD# pin is de-
asserted (high) during a read from the Local Bus. ¹
Read Data-strobe De-assertion (Motorola-type interface). Defines the
number of clock cycles after the Reference Cycle when the LBDS[3:0]#
pins are de-asserted (high) during a read from the Local Bus. ¹
Read/Write
EEPROM _PCI
W
RW
Reset
0h
W
RW
3h
(2h for
parallel port)
W
RW
0h
W
RW
2h
W
RW
0h
(1h for
parallel port)
W
RW
3h
(2h for
parallel port)
DS-0020 Jun 05
Page 32