OXMPCI952 Datasheet, PDF (26/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
OXmPCI952
5.3 Accessing logical functions
Access to the two UARTs, the Local Bus and the Parallel Port is achieved via standard I/O and Memory mapping, at addresses
defined by the Base Address Registers (BARs) in the PCI configuration space. The BARs are configured by the system to
allocate blocks of I/O and Memory space to the logical functions, according to the size required by the function. The addresses
allocated can then be used to access the functions. The mapping of these BARs, which is dependent upon the mode of the
device, is shown by the following tables.
BAR Function 0
Dual UARTs (Mode 0, Mode 1)
0
Internal UART0 (I/O Mapped)
1
Internal UART1 (I/O Mapped)
2
Unused
3
Unused
4
Local configuration registers (I/O mapped)
5
Internal UARTs/ Local configuration registers (Memory mapped)
BAR Function 1
Local bus (Mode 0)
Parallel port (Mode 1)
0
Local bus (I/O mapped)
Parallel port base registers
1
Local bus (Memory mapped)
Parallel port extended registers
2
Local configuration registers (I/O mapped)
3
Local configuration registers (Memory mapped)
4
Unused
5
Unused
5.3.1 PCI access to internal UARTs
IO and Memory Space
BAR0 and BAR1 are used to address the two UARTs
individually in I/O space, and BAR5 is used to address the
UARTs in Memory Space. The function reserves an 8-byte
block of I/O space for BAR0 and BAR1, and a 4K byte
block of memory space for BAR5. Once the I/O access and
the Memory access enable bits in the Command register
(configuration space) are set, the UARTs can accessed
according to the following tables.
UART
Address
(hex)
000
001
002
003
004
005
006
007
PCI Offset from UARTs Base Address
for Function0 in IO space (hex)
UART0
UART1
(BAR0)
(BAR1)
00
00
01
01
02
02
03
03
04
04
05
05
06
06
07
07
UART
Address
000
001
002
003
004
005
006
007
PCI Offset from Base Address 5 for
Function0 in Memory space (hex)
UART0
UART1
00
20
04
24
08
28
0C
2C
10
30
14
34
18
38
1C
3C
Note that the local registers in memory space occupy the same Base
Address Register (BAR5) as the internal Dual UARTs in Memory Space.
Bit 7 selects the region to be accessed. Access to addresses 00h to 3Ch
will be directed to the internal UARTs, and access to addresses 80h to
FCh will be directed to the local registers. When accessing the local
registers via BAR5 (bit 7 set) Fields 6:2 Define the BYTE offset for the
local registers. Eg 00000b for the LCC register, 00100b for the MIC
register)
In both cases, fields 1:0 are not utilised and are to be set to zeros. This is
because a DWORD is used to hold a single Byte, in Memory Space
DS-0020 Jun 05
Page 26