OXMPCI952 Datasheet, PDF (72/108 Pages) Oxford Semiconductor – Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.

OXFORD SEMICONDUCTOR LTD.
7.3 Configuration & Programming
The configuration registers for the local bus controller are
described in sections 5.4.3 & 5.4.4. The values of these
registers after reset allow the host system to identify the
function and configure its base address registers.
Alternatively many of the default values can be re-
programmed during device initialisation through use of the
optional serial EEPROM (see section 9).
The I/O space block can be varied in size from 4 bytes to
256 bytes (32 bytes is the default) by setting LT2[22:20]
accordingly. Varying the block size means the I/O space
can be allocated efficiently by the system, whatever the
application.
The I/O block can then be divided into one, two or four
chip-select regions, depending on the setting in LT2[26:23].
To divide the area into a four chip-select region, the user
should select the second uppermost non-zero address bit
as the Lower-Address-CS-decode. To divide into two
regions, the user should select the uppermost address bit.
If an address bit beyond the selected range is selected, the
OXmPCI952
entire I/O space is allocated to CS0#. For example, if 32
bytes of I/O space are reserved, the active address lines
are A[4:0]. To divide this into four regions, the Lower
Address CS Decode parameter should be set to A3, by
programming the value ‘0001’ into LT2[26:23]. To select
two regions, choose A4, and to maintain one region, select
any value greater than A4.
The memory space block is always 4K bytes, and always
divided into four chip-select regions of 1K byte each.
A soft reset facility is provided so software can
independently reset the peripherals on the local bus. The
local bus reset signals, LBRST and LBRST#, are always
active during a PCI bus reset and also when the
configuration register bit LT2[29] is set to 1.
The clock enable bit, when set, enables a copy of the PCI
bus clock output on the local bus pin LBCLK. A buffered
UART clock can also be asserted on the UART_Clk_Out
pin. This means that a single oscillator can be used to drive
serial ports on the local bus as well as the internal UARTs.
DS-0020 Jun 05
Page 72