PIC17C75X Datasheet, PDF (96/320 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers

PIC17C75X
TABLE 13-3: SUMMARY OF TIMER1 AND TIMER2 REGISTERS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other resets
(Note1)
16h, Bank 3
17h, Bank 3
TCON1
TCON2
CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
16h, Bank 7 TCON3
10h, Bank 2 TMR1
11h, Bank 2 TMR2
16h, Bank 1 PIR1
17h, Bank 1 PIE1
07h, Unbanked INTSTA
— CA4OVF
Timer1’s register
Timer2’s register
RBIF TMR3IF
RBIE TMR3IE
PEIF T0CKIF
CA3OVF
TMR2IF
TMR2IE
T0IF
CA4ED1 CA4ED0 CA3ED1 CA3ED0
TMR1IF
TMR1IE
INTF
CA2IF
CA2IE
PEIE
CA1IF
CA1IE
T0CKIE
TX1IF
TX1IE
T0IE
PWM3ON
RC1IF
RC1IE
INTE
-000 0000 -000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0010 0000 0010
0000 0000 0000 0000
0000 0000 0000 0000
06h, Unbanked CPUSTA
—
—
STKAV GLINTD TO
PD
POR
BOR --11 1100 --11 qq11
14h, Bank 2 PR1
Timer1 period register
xxxx xxxx uuuu uuuu
15h, Bank 2 PR2
Timer2 period register
xxxx xxxx uuuu uuuu
10h, Bank 3 PW1DCL DC1
DC0
—
—
—
—
—
—
xx-- ---- uu-- ----
11h, Bank 3 PW2DCL DC1
DC0 TM2PW2
—
—
—
—
—
xx0- ---- uu0- ----
10h, Bank 7 PW3DCL DC1
DC0 TM2PW3
—
—
—
—
—
xx0- ---- uu0- ----
12h, Bank 3 PW1DCH DC9
DC8
DC7
DC6
DC5
DC4
DC3
DC2
xxxx xxxx uuuu uuuu
13h, Bank 3 PW2DCH DC9
DC8
DC7
DC6
DC5
DC4
DC3
DC2
xxxx xxxx uuuu uuuu
11h, Bank 7 PW3DCH DC9
DC8
DC7
DC6
DC5
DC4
DC3
DC2
xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', q - value depends on condition,
shaded cells are not used by Timer1 or Timer2.
Note 1: Other (non power-up) resets include: external reset through MCLR and WDT Timer Reset.
DS30264A-page 96
Preliminary
© 1997 Microchip Technology Inc.