PIC17C75X Datasheet, PDF (141/320 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers

15.2.3 MASTER MODE
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a reset or when the SSP module is dis-
abled. Control of the I²C bus may be taken when the P
bit is set, or the bus is idle with both the S and P bits
clear.
In master mode, the SCL and SDA lines are manipu-
lated by the SSP hardware.
PIC17C75X
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
FIGURE 15-20: SSP BLOCK DIAGRAM (I²C MASTER MODE)
Read
Internal
data bus
Write
SSPBUF
SDA
SDA in
SSPSR
MSb
shift
clock
LSb
Start bit, Stop bit,
Acknowledge
Generate
SCL
SSPM3:SSPM0
SSPADD<6:0>
Baud
rate
generator
SCL in
Bus Collision
Start bit detect,
Stop bit detect
Write collision detect
Clock Arbitration
State counter for
end of XMIT/RCV
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
© 1997 Microchip Technology Inc.
Preliminary
DS30264A-page 141