PIC17C75X Datasheet, PDF (80/320 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers

PIC17C75X
10.7 PORTG and DDRG Registers
PORTG is an 8-bit wide bi-directional port. The corre-
sponding data direction register is DDRG. A '1' in
DDRG configures the corresponding port pin as an
input. A '0' in the DDRG register configures the corre-
sponding port pin as an output. Reading PORTG
reads the status of the pins, whereas writing to them
will write to the respective port latch.
The lower four bits of PORTG are multiplexed with four
of the 12 channels of the 10-bit A/D converter.
The remaining bits of PORTG are multiplexed with
peripheral output and inputs. RG4 is multiplexed with
the CAP3 input, RG5 is multiplexed with the PWM3
output, RG6 and RG7 are multiplexed with the
USART2 functions.
Upon reset the entire Port is automatically configured
as analog inputs, and must be configured in software
to be a digital I/O.
Example 10-7 shows the instruction sequence to initial-
ize PORTG. The Bank Select Register (BSR) must be
selected to Bank 5 for the port to be initialized. The fol-
lowing example uses the MOVLB instruction to load the
BSR register for bank selection.
EXAMPLE 10-7: INITIALIZING PORTG
MOVLB
MOVLW
MOVPF
CLRF
MOVLW
MOVWF
5
; Select Bank 5
0x0E ; Configure PORTG as
ADCON1 ; digital
PORTG ; Initialize PORTG data
; latches before setting
; the data direction
; register
0x03 ; Value used to initialize
; data direction
DDRG ; Set RG<1:0> as inputs
; RG<7:2> as outputs
FIGURE 10-14: BLOCK DIAGRAM OF RG3:RG0
Data bus
WR PORTG
D
Q
CK Q
Data Latch
WR DDRG
D
Q
CK Q
DDRG Latch
RD PORT
RD DDRG
Q
D
EENN
VDD
P
I/O pin
N
VSS
ST
input
buffer
PCFG3:PCFG0
VAN
To other pads
CHS3:CHS0
To other pads
DS30264A-page 80
Preliminary
© 1997 Microchip Technology Inc.