PIC17C75X Datasheet, PDF (120/320 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers

PIC17C75X
TABLE 14-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Address
Name
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other resets
(Note1)
16h, Bank 1 PIR1
RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF
RC1IF 0000 0010 0000 0010
17h, Bank 1 PIE1
RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE
RC1IE 0000 0000 0000 0000
13h, Bank 0 RCSTA1
SPEN
RX9 SREN CREN
—
FERR OERR
RX9D 0000 -00x 0000 -00u
14h, Bank 0 RCREG1
RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0
xxxx xxxx uuuu uuuu
15h, Bank 0 TXSTA1
CSRC
TX9 TXEN SYNC
—
—
TRMT
TX9D 0000 --1x 0000 --1u
17h, Bank 0 SPBRG1 Baud rate generator register
xxxx xxxx uuuu uuuu
10h, Bank 4 PIR2
SSPIF BCLIF ADIF
— CA4IF CA3IF TX2IF
RC2IF 000- 0010 000- 0010
11h, Bank 4 PIE2
SSPIE BCLIE ADIE
— CA4IE CA3IE TX2IE
RC2IE 000- 0000 000- 0000
13h, Bank 4 RCSTA2
SPEN
RX9 SREN CREN
—
FERR OERR
RX9D 0000 -00x 0000 -00u
14h, Bank 4 RCREG2
RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0
xxxx xxxx uuuu uuuu
15h, Bank 4 TXSTA2
CSRC
TX9 TXEN SYNC
—
—
TRMT
TX9D 0000 --1x 0000 --1u
17h, Bank 4 SPBRG2 Baud rate generator register
xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for synchronous
master reception.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
DS30264A-page 120
Preliminary
© 1997 Microchip Technology Inc.