PIC17C75X Datasheet, PDF (243/320 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers

PIC17C75X
TABLE 20-14: I²C BUS DATA REQUIREMENTS
Param.
No.
Sym Characteristic
Min
Max Units
Conditions
100
THIGH Clock high time 100 kHz mode 2(TOSC)(BRG + 1) § —
µs
400 kHz mode 2(TOSC)(BRG + 1) § —
µs
1 MHz mode ^{(1) 2(TOSC)(BRG + 1) § —}
µs
101
TLOW Clock low time 100 kHz mode 2(TOSC)(BRG + 1) § —
µs
400 kHz mode 2(TOSC)(BRG + 1) § —
µs
1 MHz mode ^{(1) 2(TOSC)(BRG + 1) § —}
µs
102
TR SDA and SCL 100 kHz mode
—
1000 * ns Cb is specified to be from
rise time
400 kHz mode
20 + 0.1Cb *
300 * ns ^{10 to 400 pF}
1 MHz mode ⁽¹⁾
—
300 * ns
103
TF SDA and SCL 100 kHz mode
—
300 * ns Cb is specified to be from
fall time
400 kHz mode
20 + 0.1Cb *
300 * ns ^{10 to 400 pF}
1 MHz mode ⁽¹⁾
—
100 * ns
90
TSU:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) § —
µs Only relevant for repeated
setup time
400 kHz mode 2(TOSC)(BRG + 1) § —
µs ^{START condition}
1 MHz mode ^{(1) 2(TOSC)(BRG + 1) § —}
µs
91
THD:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) § —
µs After this period the first
hold time
400 kHz mode 2(TOSC)(BRG + 1) § —
µs ^{clock pulse is generated}
1 MHz mode ^{(1) 2(TOSC)(BRG + 1) § —}
µs
106
THD:DAT Data input
100 kHz mode
0
—
ns
hold time
400 kHz mode
0
0.9 * µs
1 MHz mode ⁽¹⁾
TBD *
—
ns
107
TSU:DAT Data input
setup time
100 kHz mode
400 kHz mode
250 *
100 *
—
ns Note 2
—
ns
1 MHz mode ⁽¹⁾
TBD *
—
ns
92
TSU:STO STOP condition 100 kHz mode 2(TOSC)(BRG + 1) § —
µs
setup time
400 kHz mode 2(TOSC)(BRG + 1) § —
µs
1 MHz mode ^{(1) 2(TOSC)(BRG + 1) § —}
µs
109
TAA Output valid
100 kHz mode
from clock
400 kHz mode
—
3500 * ns
—
1000 * ns
1 MHz mode ⁽¹⁾
—
—
ns
110
TBUF Bus free time
100 kHz mode
400 kHz mode
1 MHz mode ⁽¹⁾
4.7 ‡
1.3 ‡
TBD *
—
µs Time the bus must be free
—
µs ^{before a new transmission}
—
µs ^{can start}
D102 ‡
Cb Bus capacitive loading
—
400 * pF
* Characterized but not tested.
§ This specification ensured by design. For the value required by the I²C specification, please refer to Figure E-11.
‡ These parameters are for design guidance only and are not tested, nor characterized.
Note 1: Maximum pin capacitance = 10 pF for all I²C pins.
2: A fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the parameter # 107 ≥ 250 ns must then
be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
Parameter # 102.+ # 107 = 1000 + 250 = 1250 ns (for 100 kHz-mode) before the SCL line is released.
© 1997 Microchip Technology Inc.
Preliminary
DS30264A-page 243