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PIC17C75X Datasheet, PDF (183/320 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers | |||
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18.0 INSTRUCTION SET SUMMARY
The PIC17CXXX instruction set consists of 58 instruc-
tions. Each instruction is a 16-bit word divided into an
OPCODE and one or more operands. The opcode
speciï¬es the instruction type, while the operand(s) fur-
ther specify the operation of the instruction. The
PIC17CXXX instruction set can be grouped into three
types:
⢠byte-oriented
⢠bit-oriented
⢠literal and control operations.
These formats are shown in Figure 18-1.
Table 18-1 shows the ï¬eld descriptions for the
opcodes. These descriptions are useful for under-
standing the opcodes in Table 18-2 and in each speciï¬c
instruction descriptions.
byte-oriented instructions, 'f' represents a ï¬le regis-
ter designator and 'd' represents a destination designa-
tor. The ï¬le register designator speciï¬es which ï¬le
register is to be used by the instruction.
The destination designator speciï¬es where the result of
the operation is to be placed. If 'd' = '0', the result is
placed in the WREG register. If 'd' = '1', the result is
placed in the ï¬le register speciï¬ed by the instruction.
bit-oriented instructions, 'b' represents a bit ï¬eld des-
ignator which selects the number of the bit affected by
the operation, while 'f' represents the number of the ï¬le
in which the bit is located.
literal and control operations, 'k' represents an 8- or
13-bit constant or literal value.
The instruction set is highly orthogonal and is grouped
into:
⢠byte-oriented operations
⢠bit-oriented operations
⢠literal and control operations
All instructions are executed within one single instruc-
tion cycle, unless:
⢠a conditional test is true
⢠the program counter is changed as a result of an
instruction
⢠a table read or a table write instruction is exe-
cuted (in this case, the execution takes two
instruction cycles with the second cycle executed
as a NOP)
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 25 MHz, the normal
instruction execution time is 160 ns. If a conditional test
is true or the program counter is changed as a result of
an instruction, the instruction execution time is 320 ns.
PIC17C75X
TABLE 18-1: OPCODE FIELD
DESCRIPTIONS
Field
Description
f Register ï¬le address (00h to FFh)
p Peripheral register ï¬le address (00h to 1Fh)
i Table pointer control i = '0' (do not change)
i = '1' (increment after instruction execution)
t Table byte select t = '0' (perform operation on lower
byte)
t = '1' (perform operation on upper byte literal ï¬eld,
constant data)
WREG Working register (accumulator)
b Bit address within an 8-bit ï¬le register
k Literal ï¬eld, constant data or label
x Don't care location (= '0' or '1')
The assembler will generate code with x = '0'. It is
the recommended form of use for compatibility with
all Microchip software tools.
d Destination select
0 = store result in WREG
1 = store result in ï¬le register f
Default is d = '1'
u Unused, encoded as '0'
s Destination select
0 = store result in ï¬le register f and in the WREG
1 = store result in ï¬le register f
Default is s = '1'
label Label name
C,DC, ALU status bits Carry, Digit Carry, Zero, Overï¬ow
Z,OV
GLINTD Global Interrupt Disable bit (CPUSTA<4>)
TBLPTR Table Pointer (16-bit)
TBLAT Table Latch (16-bit) consists of high byte (TBLATH)
and low byte (TBLATL)
TBLATL Table Latch low byte
TBLATH Table Latch high byte
TOS Top of Stack
PC Program Counter
BSR Bank Select Register
WDT Watchdog Timer Counter
TO Time-out bit
PD Power-down bit
dest Destination either the WREG register or the speci-
ï¬ed register ï¬le location
[ ] Options
( ) Contents
â Assigned to
< > Register bit ï¬eld
â In the set of
italics User deï¬ned term (font is courier)
© 1997 Microchip Technology Inc.
DS30264A-page 183
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