PIC17C75X Datasheet, PDF (23/320 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers

PIC17C75X
5.1.4 TIME-OUT SEQUENCE
On power-up the time-out sequence is as follows: First
the internal POR signal goes high when the POR trip
point is reached. If MCLR is high, then both the OST
and PWRT timers start. In general the PWRT time-out
is longer, except with low frequency crystals/resona-
tors. The total time-out also varies based on oscillator
configuration. Table 5-1 shows the times that are asso-
ciated with the oscillator configuration. Figure 5-5 and
Figure 5-6 display these time-out sequences.
If the device voltage is not within electrical specification
at the end of a time-out, the MCLR/VPP pin must be
held low until the voltage is within the device specifica-
tion. The use of an external RC delay is sufficient for
many of these applications.
The time-out sequence begins from the first rising edge
of MCLR.
Table 5-3 shows the reset conditions for some special
registers, while Table 5-4 shows the initialization condi-
tions for all the registers.
TABLE 5-1: TIME-OUT IN VARIOUS SITUATIONS
Oscillator
Configuration
XT, LF
EC, RC
Power-up
Greater of: 96 ms or 1024TOSC
Greater of: 96 ms or 1024TOSC
TABLE 5-2: STATUS BITS AND THEIR SIGNIFICANCE
POR _BOR ⁽¹⁾
TO
PD
Wake up from
SLEEP
1024TOSC
—
Event
MCLR Reset
—
—
BOR
—
—
0
0
1
1 Power-on Reset
1
1
1
0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP
1
1
0
1 WDT Reset during normal operation
1
1
0
0 WDT Wake-up during SLEEP
1
1
1
1 MCLR Reset during normal operation
1
0
x
x Brown-out Reset
0
0
0
x Illegal, TO is set on POR
0
0
x
0 Illegal, PD is set on POR
x
x
1
1
CLRWDT instruction executed
Note 1: When BOR is enabled, else the BOR status bit is unknown
TABLE 5-3: RESET CONDITION FOR THE PROGRAM COUNTER AND THE CPUSTA REGISTER
Event
PCH:PCL
CPUSTA ⁽⁴⁾
OST Active
Power-on Reset
0000h
--11 1100
Yes
Brown-out Reset
0000h
--11 1101
No
MCLR Reset during normal operation
0000h
--11 1111
No
MCLR Reset during SLEEP
0000h
--11 1011
Yes ⁽²⁾
WDT Reset during normal operation
0000h
--11 0111
No
WDT Wake-up during SLEEP ⁽³⁾
0000h
--11 0011
Yes ⁽²⁾
Interrupt wake-up from SLEEP GLINTD is set
PC + 1
--11 1011
Yes ⁽²⁾
GLINTD is clear
PC + 1 ⁽¹⁾
--10 1011
Yes ⁽²⁾
Legend: u = unchanged, x = unknown, - = unimplemented read as '0'.
Note 1: On wake-up, this instruction is executed. The instruction at the appropriate interrupt vector is fetched and
then executed.
2: The OST is only active when the Oscillator is configured for XT or LF modes.
3: The Program Counter = 0, that is, the device branches to the reset vector. This is different from the
mid-range devices.
4: When BOR is enabled, else the BOR status bit is unknown.
© 1997 Microchip Technology Inc.
Preliminary
DS30264A-page 23