PIC17C75X Datasheet, PDF (157/320 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers

15.2.12 STOP CONDITION TIMING
A stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit PEN (SSPCON2<2>). At the end of a receive/trans-
mit the SCL line is held low after the falling edge of the
ninth clock. When the PEN bit is set, the master will
assert the SDA line low . When the SDA line is sam-
pled low, the baud rate generator is reloaded and
counts down to 0. When the baud rate generator
times out, the SCL pin will be brought high, and one
T_BRG (baud rate generator rollover count) later, the
SDA pin will be de-asserted. When the SDA pin is
sampled high while SCL is high, the PEN bit will be
automatically cleared, and the P bit (SSPSTAT<4>) is
set which in turn will set the SSPIF flag. (Figure 15-34)
PIC17C75X
Whenever the CPU decides to take control of the bus,
it will first determine if the bus is busy by checking the
S and P bits in the SSPSTAT register. If the bus is
busy, then the CPU can be interrupted (notified) when
a Stop bit is detected (i.e. bus is free).
15.2.12.1 WCOL STATUS FLAG
If the user writes the SSPBUF when a STOP
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 15-34: STOP CONDITION RECEIVE OR TRANSMIT MODE
Write to SSPCON2
Set PEN
Falling edge of
9th clock
SCL
T_BRG
SCL = 1 for T_BRG, followed by SDA = 1 for T_BRG
after SDA sampled high, PEN bit (SSPCON2<2>) is
automatically cleared. P bit (SSPSTAT<4>) is set
SDA
ACK
T_BRG
T_BRG
P
T_BRG
SCL brought high after T_BRG
SDA asserted low before rising edge of clock
to setup stop condition.
Note: T_BRG = one baud rate generator period.
© 1997 Microchip Technology Inc.
Preliminary
DS30264A-page 157