PIC17C75X Datasheet, PDF (239/320 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers

PIC17C75X
FIGURE 20-11: SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
SCK
(CKP = 1)
SDO
80
MSB
79
BIT6 - - - - - -1
SDI
MSB IN
74
73
Refer to Figure 20-1 for load conditions.
75, 76
BIT6 - - - -1
83
79
78
LSB
77
LSB IN
TABLE 20-11: SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)
Param.
No.
Sym
Characteristic
Min
Typ† Max Units Conditions
70
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TCY *
—
—
ns
71
TscH
SCK input high time (slave mode) TCY + 20 * —
—
ns
72
TscL
SCK input low time (slave mode) TCY + 20 * —
—
ns
73
TdiV2scH, Setup time of SDI data input to SCK 100 *
—
—
ns
TdiV2scL
edge
74
TscH2diL, Hold time of SDI data input to SCK
100 *
—
—
ns
TscL2diL
edge
75
TdoR
SDO data output rise time
—
10
25 *
ns
76
TdoF
SDO data output fall time
—
10
25 *
ns
77
TssH2doZ SS↑ to SDO output hi-impedance
10 *
—
50 *
ns
78
TscR
SCK output rise time (master mode)
—
10
25 *
ns
79
TscF
SCK output fall time (master mode)
—
10
25 *
ns
80
TscH2doV, SDO data output valid after SCK
—
—
50 *
ns
TscL2doV edge
83
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5TCY
—
—
ns
+ 40 *
* Characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
© 1997 Microchip Technology Inc.
Preliminary
DS30264A-page 239