PIC17C75X Datasheet, PDF (246/320 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers

PIC17C75X
FIGURE 20-17: A/D CONVERSION TIMING
BSF ADCON0, GO
Q4
A/D CLK ¹³²
A/D DATA
(TOSC/2) ⁽¹⁾
1 TCY
131
130
9
8
7 ^{... ...} 2
1
0
ADRES
ADIF
GO
OLD_DATA
NEW_DATA
DONE
SAMPLE
SAMPLING STOPPED
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
TABLE 20-18: A/D CONVERSION REQUIREMENTS
Param.
No.
130
131
132
Sym Characteristic
Min Typ†
TAD A/D clock period
PIC17CXXX
1.6
—
PIC17LCXXX
3.0
—
PIC17CXXX
2.0 *
4.0
PIC17LCXXX
3.0 *
6.0
TCNV Conversion time
12 §
—
(not including acquisition time) (Note 1)
TACQ Acquisition time
(Note 2) 40
Max Units
Conditions
—
—
6.0 *
9.0 *
13 §
µs TOSC based, VREF ≥ 3.0V
µs TOSC based, VREF full range
µs A/D RC Mode
µs A/D RC Mode
TAD
—
µs
10 *
—
—
µs The minimum time is the
amplifier settling time. This
may be used if the “new”
input voltage has not
changed by more than 1LSb
(i.e. 5mV @ 5.12V) from the
last sampled voltage (as
stated on CHOLD).
134
TGO Q4 to ADCLK start
— Tosc/2 § —
— If the A/D clock source is
selected as RC, a time of
TCY is added before the A/D
clock starts. This allows the
sleep instruction to be exe-
cuted.
*
†
§
Note 1:
2:
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
This specification ensured by design.
ADRES register may be read on the following TCY cycle.
See Section 16.1 for minimum conditions when input voltage has changed more then 1 LSb.
DS30264A-page 246
Preliminary
© 1997 Microchip Technology Inc.