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PIC17C75X Datasheet, PDF (272/320 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers | |||
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PIC17C75X
FIGURE E-12: I2C BUS DATA TIMING SPECIFICATION
103
100
101
SCL
SDA
In
90
91
106
107
109
109
SDA
Out
102
92
110
TABLE E-3: I2C BUS DATA TIMING SPECIFICATION
Microchip
Parameter
No.
Sym
Characteristic
Min
Max Units
Conditions
100
THIGH Clock high time
100 kHz mode
4.0
â
µs
400 kHz mode
0.6
â
µs
101
TLOW Clock low time
100 kHz mode
4.7
â
µs
400 kHz mode
1.3
â
µs
102
TR SDA and SCL rise
100 kHz mode
â
1000 ns
time
400 kHz mode 20 + 0.1Cb 300
ns Cb is speciï¬ed to be from
10 to 400 pF
103
TF SDA and SCL fall time 100 kHz mode
â
300
ns
400 kHz mode 20 + 0.1Cb 300
ns Cb is speciï¬ed to be from
10 to 400 pF
90
TSU:STA START condition
setup time
100 kHz mode
400 kHz mode
4.7
â
µs Only relevant for repeated
0.6
â
µs START condition
91
THD:STA START condition hold 100 kHz mode
time
400 kHz mode
4.0
â
µs After this period the ï¬rst clock
0.6
â
µs pulse is generated
106
THD:DAT Data input hold time 100 kHz mode
0
â
ns
400 kHz mode
0
0.9
µs
107
TSU:DAT Data input setup time 100 kHz mode
250
â
ns Note 2
400 kHz mode
100
â
ns
92
TSU:STO STOP condition setup 100 kHz mode
time
400 kHz mode
4.7
â
µs
0.6
â
µs
109
TAA Output valid from
100 kHz mode
clock
400 kHz mode
â
3500 ns Note 1
â
1000 ns
110
TBUF Bus free time
100 kHz mode
400 kHz mode
4.7
â
µs Time the bus must be free
1.3
â
µs before a new transmission
can start
D102
Cb Bus capacitive loading
â
400 pF
Note 1:
2:
As a transmitter, the device must provide this internal minimum delay time to bridge the undeï¬ned region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tsu;DAT ⥠250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus speciï¬cation) before the SCL line is
released.
DS30264A-page 272
Preliminary
© 1997 Microchip Technology Inc.
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