PIC17C75X Datasheet, PDF (134/320 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers

PIC17C75X
15.2 SSP I²C Operation
The SSP module in I²C mode fully implements all mas-
ter and slave functions (including general call support)
and provides interrupts on start and stop bits in hard-
ware to determine a free bus (multi-master function).
The SSP module implements the standard mode spec-
ifications as well as 7-bit and 10-bit addressing.
Appendix E gives an overview of the I²C bus specifica-
tion.
FIGURE 15-13: SSP BLOCK DIAGRAM
(I²C MODE)
Read
Internal
data bus
Write
SCL
SDA
SSPBUF reg
shift
clock
SSPSR reg
MSb
LSb
Match detect
Addr Match
SSPADD reg
Start and
Stop bit detect
Set, Reset
S, P bits
(SSPSTAT reg)
FIGURE 15-14: I²C MASTER MODE BLOCK
DIAGRAM
Read
SSPADD<6:0>
7
Baud Rate Generator
Internal
data bus
Write
SCL
SDA
SSPBUF reg
shift
clock
SSPSR reg
MSb
LSb
Match detect
Addr Match
SSPADD reg
Start and Stop bit
detect / generate
Set/Clear S bit
and
Clear/Set P, bits
(SSPSTAT reg)
and Set SSPIF
Two pins are used for data transfer. These are the SCL
pin, which is the clock, and the SDA pin, which is the
data. Pins that are on PortA are automatically config-
ured when the I²C mode is enabled. The SSP module
functions are enabled by setting SSP Enable bit
SSPEN (SSPCON1<5>).
The SSP module has six registers for I²C operation.
These are the:
• SSP Control Register1 (SSPCON1)
• SSP Control Register2 (SSPCON2)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly acces-
sible
• SSP Address Register (SSPADD)
The SSPCON1 register allows control of the I²C oper-
ation. Four mode selection bits (SSPCON1<3:0>)
allow one of the following I²C modes to be selected:
• I²C Slave mode (7-bit address)
• I²C Slave mode (10-bit address)
• I²C Master mode, clock = OSC/4 (SSPADD +1)
Selection of any I²C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open drain. These
pins are on PORTA and therefore there is no need to
program to be inputs.
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START or STOP bit, specifies if the received byte was
data or address if the next byte is the completion of
10-bit address, and if this will be a read or write data
transfer.
The SSPBUF is the register to which transfer data is
written to or read from. The SSPSR register shifts the
data in or out of the device. In receive operations, the
SSPBUF and SSPSR create a doubled buffered
receiver. This allows reception of the next byte to begin
before reading the last byte of received data. When the
complete byte is received, it is transferred to the
SSPBUF register and flag bit SSPIF is set. If another
complete byte is received before the SSPBUF register
is read, a receiver overflow has occurred and bit
SSPOV (SSPCON1<6>) is set and the byte in the
SSPSR is lost.
The SSPADD register holds the slave address. In
10-bit mode, the user needs to write the high byte of the
address (1111 0 A9 A8 0). Following the high byte
address match, the low byte of the address needs to be
loaded (A7:A0).
DS30264A-page 134
Preliminary
© 1997 Microchip Technology Inc.