PIC17C75X Datasheet, PDF (38/320 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers

PIC17C75X
EXAMPLE 6-2: SAVING STATUS AND WREG IN RAM (NESTED)
; The addresses that are used to store the CPUSTA and WREG values must be in the data memory
; address range of 1Ah - 1Fh. Up to 6 locations can be saved and restored using the MOVFP
; instruction. This instruction neither affects the status bits, nor corrupts the WREG register.
; This routine uses the FRS0, so it controls the FS1 and FS0 bits in the ALUSTA register.
;
Nobank_FSR
EQU 0x40
Bank_FSR
EQU 0x41
ALU_Temp
EQU 0x42
WREG_TEMP
EQU 0x43
BSR_S1
EQU 0x01A
; 1st location to save BSR
BSR_S2
EQU 0x01B
; 2nd location to save BSR (Label Not used in program)
BSR_S3
EQU 0x01C
; 3rd location to save BSR (Label Not used in program)
BSR_S4
EQU 0x01D
; 4th location to save BSR (Label Not used in program)
BSR_S5
EQU 0x01E
; 5th location to save BSR (Label Not used in program)
BSR_S6
EQU 0x01F
; 6th location to save BSR (Label Not used in program)
;
INITIALIZATION
;
CALL CLEAR_RAM
; Must Clear all Data RAM
;
INIT_POINTERS
; Must Initialize the pointers for POP and PUSH
CLRF BSR, F
; Set All banks to 0
CLRF ALUSTA, F
; FSR0 post increment
BSF
ALUSTA, FS1
CLRF WREG, F
; Clear WREG
MOVLW BSR_S1
; Load FSR0 with 1st address to save BSR
MOVWF FSR0
MOVWF Nobank_FSR
MOVLW 0x20
MOVWF Bank_FSR
:
:
; Your code
:
:
; At Interrupt Vector Address
PUSH BSF
ALUSTA, FS0
; FSR0 has auto-increment, does not affect status bits
BCF
ALUSTA, FS1
; does not affect status bits
MOVFP BSR, INDF0
; No Status bits are affected
CLRF BSR, F
; Periperal and Data RAM Bank 0 No Status bits are affected
MOVPF ALUSTA, ALU_Temp ;
MOVPF FSR0, Nobank_FSR ; Save the FSR for BSR values
MOVPF WREG, WREG_TEMP ;
MOVFP Bank_FSR, FSR0
; Restore FSR value for other values
MOVFP ALU_Temp, INDF0 ; Push ALUSTA value
MOVFP WREG_TEMP, INDF0 ; Push WREG value
MOVFP PCLATH, INDF0
; Push PCLATH value
MOVPF FSR0, Bank_FSR
; Restore FSR value for other values
MOVFP Nobank_FSR, FSR0 ;
;
:
; Interrupt Service Routine (ISR) code
;
POP
CLRF ALUSTA, F
; FSR0 has auto-decrement, does not affect status bits
MOVFP Bank_FSR, FSR0
; Restore FSR value for other values
DECF FSR0, F
;
MOVFP INDF0, PCLATH
; Pop PCLATH value
MOVFP INDF0, WREG
; Pop WREG value
BSF
ALUSTA, FS1
; FSR0 does not change
MOVPF INDF0, ALU_Temp ; Pop ALUSTA value
MOVPF FSR0, Bank_FSR
; Restore FSR value for other values
DECF Nobank_FSR, F
;
MOVFP Nobank_FSR, FSR0 ; Save the FSR for BSR values
MOVFP ALU_Temp, ALUSTA ;
MOVFP INDF0, BSR
; No Status bits are affected
;
RETFIE
; Return from interrupt (enable interrupts)
DS30264A-page 38
Preliminary
© 1997 Microchip Technology Inc.