PIC17C75X Datasheet, PDF (144/320 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers

PIC17C75X
15.2.7 I²C MASTER MODE START CONDITION
TIMING
To initiate a START condition the user sets the start
condition enable bit or SEN bit (SSPCON2<0>). If the
SDA and SCL pins are sampled high, the baud rate
generator is re-loaded with the contents of
SSPADD<6:0>, and starts its count. If SCL and SDA
are both sampled high when the baud rate generator
times out (T_BRG), the SDA pin is driven low. The action
of the SDA being driven low while SCL is high is the
START condition, and causes the S bit (SSPSTAT<3>)
to be set. Since the I²C module is configured in master
mode, a '1' in the S bit causes the SSPIF flag to be
set. Following this, the baud rate generator is reloaded
with the contents of SSPADD<6:0> and resumes its
count. When the baud rate generator times out (T_BRG)
the SEN bit in the SSPCON2 register will be automati-
cally cleared, the baud rate generator is suspended
leaving the SDA line held low, and the START condi-
tion is complete.
Note:
If at the beginning of START condition the
SDA and SCL pins are already sampled
low, or if during the START condition the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag (BCLIF) is
set, the START condition is aborted, and
the I²C module is reset into its IDLE state.
15.2.7.1 WCOL STATUS FLAG
If the user writes the SSPBUF when an START
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
condition is complete.
FIGURE 15-23: FIRST START BIT TIMING
Write to SSPCON2<0> occurs here.
SDA = 1,
SCL = 1
Set S bit (SSPSTAT<3>)
At completion of start bit,
automatic clear SSPCON2<0>
SDA
SCL
T_BRG
T_BRG
S
Write to SSPBUF occurs here
1st Bit
2nd Bit
T_BRG
T_BRG
DS30264A-page 144
Preliminary
© 1997 Microchip Technology Inc.