PIC17C75X Datasheet, PDF (136/320 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers

PIC17C75X
15.2.1.2 SLAVE RECEPTION
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow con-
dition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON1<6>) is set.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR2<7>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
Note:
The SSPBUF will be loaded if the SSPOV
bit = 1 and the BF flag = 0. If a read of the
SSPBUF was performed, but the user did
not clear the state of the SSPOV bit before
the next receive occured. The ACK is not
sent and the SSPBUF is updated.
15.2.1.3 SLAVE TRANSMISSION
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and the SCLpin is held low. The
transmit data must be loaded into the SSPBUF register,
which also loads the SSPSR register. Then SCL pin
should be enabled by setting bit CKP (SSPCON1<4>).
The master must monitor the SCL pin prior to asserting
another clock pulse. The slave devices may be holding
off the master by stretching the clock. The eight data
bits are shifted out on the falling edge of the SCL input.
This ensures that the SDA signal is valid during the
SCL high time (Figure 15-16).
FIGURE 15-15: I²C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
SDA
Receiving Address R/W=0
Receiving Data
ACK
Receiving Data
ACK
A7 A6 A5 A4 A3 A2 A1
ACK _{D7 D6 D5 D4 D3 D2 D1 D0}
D7 D6 D5 D4 D3 D2 D1 D0
SCL S ^{1 2 3 4} 5 ^{6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9}
P
SSPIF (PIR2<7>)
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
Cleared in software
SSPBUF register is read
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
Bus Master
terminates
transfer
FIGURE 15-16: I²C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
SDA
Receiving Address
R/W = 1
A7 A6 A5 A4 A3 A2 A1
ACK
Transmitting Data ACK
D7 D6 D5 D4 D3 D2 D1 D0
SCL
S
1 23456789
1234 56789
Data in
SCL held low
P
sampled
while CPU
responds to SSPIF
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
cleared in software
From SSP interrupt
SSPBUF is written in software service routine
CKP (SSPCON1<4>)
Set bit after writing to SSPBUF
(the SSPBUF must be written-to
before the CKP bit can be set)
DS30264A-page 136
Preliminary
© 1997 Microchip Technology Inc.