PIC17C75X Datasheet, PDF (49/320 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers

7.2.2.3 TMR0 STATUS/CONTROL REGISTER
(T0STA)
This register contains various control bits. Bit7
(INTEDG) is used to control the edge upon which a sig-
nal on the RA0/INT pin will set the RA0/INT interrupt
flag. The other bits configure the Timer0 prescaler and
clock source.
PIC17C75X
FIGURE 7-8: T0STA REGISTER (ADDRESS: 05h, UNBANKED)
R/W - 0 R/W - 0
INTEDG T0SE
bit7
R/W - 0
T0CS
R/W - 0
T0PS3
R/W - 0
T0PS2
R/W - 0
T0PS1
R/W - 0
T0PS0
bit 7:
INTEDG: RA0/INT Pin Interrupt Edge Select bit
This bit selects the edge upon which the interrupt is detected.
1 = Rising edge of RA0/INT pin generates interrupt
0 = Falling edge of RA0/INT pin generates interrupt
U-0
—
bit0
R = Readable bit
W = Writable bit
U = Unimplemented,
reads as ‘0’
-n = Value at POR reset
bit 6:
T0SE: Timer0 Clock Input Edge Select bit
This bit selects the edge upon which TMR0 will increment.
When T0CS = 0 (External Clock)
1 = Rising edge of RA1/T0CKI pin increments TMR0 and/or generates a T0CKIF interrupt
0 = Falling edge of RA1/T0CKI pin increments TMR0 and/or generates a T0CKIF interrupt
When T0CS = 1 (Internal Clock)
Don’t care
bit 5:
T0CS: Timer0 Clock Source Select bit
This bit selects the clock source for Timer0.
1 = Internal instruction clock cycle (TCY)
0 = External clock input on the T0CKI pin
bit 4-1: T0PS3:T0PS0: Timer0 Prescale Selection bits
These bits select the prescale value for Timer0.
T0PS3:T0PS0 Prescale Value
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
bit 0: Unimplemented: Read as '0'
© 1997 Microchip Technology Inc.
Preliminary
DS30264A-page 49