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PIC17C75X Datasheet, PDF (179/320 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers | |||
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PIC17C75X
17.3 Watchdog Timer (WDT)
17.3.2 CLEARING THE WDT AND POSTSCALER
The Watchdog Timerâs function is to recover from
software malfunction. The WDT uses an internal free
running on-chip RC oscillator for its clock source. This
does not require any external components. This RC
oscillator is separate from the RC oscillator of the
OSC1/CLKIN pin. That means that the WDT will run,
even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins have been stopped, for example,
by execution of a SLEEP instruction. During normal
operation and SLEEP mode, a WDT time-out
generates a device RESET. The WDT can be
permanently disabled by programming the conï¬gura-
tion bits WDTPS1:WDTPS0 as '00' (Section 17.1).
Under normal operation, the WDT must be cleared on
a regular interval. This time is less the minimum WDT
overï¬ow time. Not clearing the WDT in this time frame
will cause the WDT to overï¬ow and reset the device.
17.3.1 WDT PERIOD
The WDT has a nominal time-out period of 12 ms, (with
postscaler = 1). The time-out periods vary with temper-
ature, VDD and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
postscaler with a division ratio of up to 1:256 can be
assigned to the WDT. Thus, typical time-out periods up
to 3.0 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler (if assigned to the WDT) and pre-
vent it from timing out thus generating a device RESET
condition.
The TO bit in the CPUSTA register will be cleared upon
a WDT time-out.
The WDT and postscaler are cleared when:
⢠The device is in the reset state
⢠A SLEEP instruction is executed
⢠A CLRWDT instruction is executed
⢠Wake-up from SLEEP by an interrupt
The WDT counter/postscaler will start counting on the
ï¬rst edge after the device exits the reset state.
17.3.3 WDT PROGRAMMING CONSIDERATIONS
It should also be taken in account that under worst case
conditions (VDD = Min., Temperature = Max., max.
WDT postscaler) it may take several seconds before a
WDT time-out occurs.
The WDT and postscaler is the Power-up Timer during
the Power-on Reset sequence.
17.3.4 WDT AS NORMAL TIMER
When the WDT is selected as a normal timer, the clock
source is the device clock. Neither the WDT nor the
postscaler are directly readable or writable. The over-
ï¬ow time is 65536 TOSC cycles. On overï¬ow, the TO bit
is cleared (device is not reset). The CLRWDT instruction
can be used to set the TO bit. This allows the WDT to
be a simple overï¬ow timer. The simple timer does not
increment when in sleep.
FIGURE 17-2: WATCHDOG TIMER BLOCK DIAGRAM
On-chip RC
Oscillator(1)
WDT
Postscaler
WDT Enable
4 - to - 1 MUX
WDTPS1:WDTPS0
Note 1: This oscillator is separate from the external
RC oscillator on the OSC1 pin.
WDT Overï¬ow
TABLE 17-2: REGISTERS/BITS ASSOCIATED WITH THE WATCHDOG TIMER
Address
Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other resets
(Note1)
â
Conï¬g
See Figure 17-1 for location of WDTPSx bits in Conï¬guration Word.
(Note 2)
(Note 2)
06h, Unbanked CPUSTA
â
â
STKAV GLINTD
TO
PD
POR
BOR --11 1100
Legend: - = unimplemented read as '0', q - value depends on condition, shaded cells are not used by the WDT.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
2: This value will be as the device was programmed, or if unprogrammed, will read as all '1's.
--11 qq11
© 1997 Microchip Technology Inc.
Preliminary
DS30264A-page 179
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