PIC17C75X Datasheet, PDF (248/320 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers

PIC17C75X
FIGURE 20-19: MEMORY INTERFACE READ TIMING
Q1
Q2
Q3
Q4
Q1
OSC1
ALE
OE
AD<15:0>
'1'
WR
166
164
168
160
165
Addr out
150
151
167
Data in
162
163
Q2
161
Addr out
'1'
TABLE 20-20: MEMORY INTERFACE READ REQUIREMENTS
Param.
No. Sym
Characteristic
Min
Typ†
Max
Units Conditions
150 TadV2alL AD15:AD0 (address) valid to PIC17CXXX 0.25Tcy - 10
—
ALE↓ (address setup time) PIC17LCXXX
TBD
—
151 TalL2adI ALE↓ to address out invalid PIC17CXXX
5*
—
(address hold time)
PIC17LCXXX
TBD
—
—
ns
—
—
ns
—
160 TadZ2oeL AD15:AD0 hi-impedance to PIC17CXXX
0*
—
OE↓
PIC17LCXXX
TBD
—
—
ns
—
161 ToeH2adD OE↑ to AD15:AD0 driven
PIC17CXXX 0.25Tcy - 15
—
PIC17LCXXX
TBD
—
—
ns
—
162 TadV2oeH Data in valid before OE↑
PIC17CXXX
35
—
(data setup time)
PIC17LCXXX
TBD
—
—
ns
—
163 ToeH2adI OE↑to data in invalid
164 TalH
(data hold time)
ALE pulse width
PIC17CXXX
0
—
PIC17LCXXX
TBD
—
—
ns
—
PIC17CXXX
—
0.25TCY §
—
ns
PIC17LCXXX
—
TBD
—
165 ToeL
OE pulse width
166 TalH2alH ALE↑ to ALE↑(cycle time)
167 Tacc
Address access time
PIC17CXXX 0.5Tcy - 35 §
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
TBD
—
—
—
—
—
—
TCY §
TBD
—
—
—
ns
—
—
ns
—
0.75TCY - 30
ns
TBD
168 Toe
Output enable access time PIC17CXXX
—
(OE low to Data Valid)
PIC17LCXXX
—
—
0.5TCY - 45
ns
—
TBD
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
DS30264A-page 248
Preliminary
© 1997 Microchip Technology Inc.