PIC17C75X Datasheet, PDF (44/320 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers

PIC17C75X
TABLE 7-3: SPECIAL FUNCTION REGISTERS
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
resets (3)
Unbanked
00h INDF0
01h FSR0
02h PCL
03h⁽¹⁾ PCLATH
04h ALUSTA
05h T0STA
Uses contents of FSR0 to address data memory (not a physical register)
Indirect data memory address pointer 0
Low order 8-bits of PC
Holding register for upper 8-bits of PC
FS3
FS2
FS1
FS0
OV
Z
DC
INTEDG T0SE
T0CS
T0PS3 T0PS2 T0PS1
T0PS0
---- ---- ---- ----
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
C
1111 xxxx 1111 uuuu
— 0000 000- 0000 000-
06h⁽²⁾
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
CPUSTA
INTSTA
INDF1
FSR1
WREG
TMR0L
TMR0H
TBLPTRL
TBLPTRH
BSR
—
—
STKAV GLINTD
TO
PD
POR
PEIF T0CKIF T0IF
INTF
PEIE T0CKIE
T0IE
Uses contents of FSR1 to address data memory (not a physical register)
Indirect data memory address pointer 1
Working register
TMR0 register; low byte
TMR0 register; high byte
Low byte of program memory table pointer
High byte of program memory table pointer
Bank select register
BOR
INTE
--11 1100 --11 qquu
0000 0000 0000 0000
---- ---- ---- ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Bank 0
10h _PORTA
11h DDRB
12h PORTB
13h RCSTA1
14h RCREG1
15h TXSTA1
16h TXREG1
17h SPBRG1
RBPU
—
RA5/TX1/ RA4/RX1/ RA3/SDI/
CK1
DT1
SDA
Data direction register for PORTB
RB7/
SDO
RB6/
SCK
RB5/
RB4/
RB3/
TCLK3 TCLK12 PWM2
SPEN RX9
SREN
CREN
—
Serial port receive register
CSRC TX9
TXEN
SYNC
—
Serial Port Transmit Register (for USART1)
Baud Rate Generator Register (for USART1)
RA2/SS/
SCL
RB2/
PWM1
FERR
—
RA1/T0CKI
RB1/
CAP2
OERR
TRMT
RA0/INT
RB0/
CAP1
RX9D
TX9D
0-xx xxxx 0-uu uuuu
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
0000 -00x 0000 -00u
xxxx xxxx uuuu uuuu
0000 --1x 0000 --1u
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Bank 1
10h DDRC
11h PORTC
12h DDRD
13h PORTD
14h DDRE
Data direction register for PORTC
RC7/
AD7
RC6/
AD6
RC5/
AD5
Data direction register for PORTD
RD7/
AD15
RD6/
AD14
RD5/
AD13
Data direction register for PORTE
RC4/
AD4
RD4/
AD12
RC3/
AD3
RD3/
AD11
RC2/
AD2
RD2/
AD10
RC1/
AD1
RD1/
AD9
RC0/
AD0
RD0/
AD8
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
---- 1111 ---- 1111
15h _PORTE
—
—
—
—
RE3/
CAP4
RE2/WR
RE1/OE RE0/ALE ---- xxxx ---- uuuu
16h PIR1
RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF
TX1IF
RC1IF x000 0010 u000 0010
17h PIE1
RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE
TX1IE
RC1IE 0000 0000 0000 0000
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. Shaded cells are unimplemented, read as '0'.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose contents are updated
from or transferred to the upper byte of the program counter.
The TO and PD status bits in CPUSTA are not affected by a MCLR reset.
Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
DS30264A-page 44
Preliminary
© 1997 Microchip Technology Inc.