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| PIC17C75X Datasheet, PDF (273/320 Pages) Microchip Technology – High-Performance 8-Bit CMOS EPROM Microcontrollers | |||
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PIC17C75X
APPENDIX F: STATUS AND CONTROL REGISTERS
FIGURE F-1: PIC17C75X REGISTER FILE MAP
Addr Unbanked
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
INDF0
FSR0
PCL
PCLATH
ALUSTA
T0STA
CPUSTA
INTSTA
INDF1
FSR1
WREG
TMR0L
TMR0H
TBLPTRL
TBLPTRH
BSR
Bank 0
Bank 1 (1) Bank 2 (1)
Bank 3 (1)
Bank 4 (1)
10h
PORTA
11h
DDRB
12h PORTB
13h RCSTA1
14h RCREG1
15h TXSTA1
16h TXREG1
17h SPBRG1
Unbanked
DDRC
PORTC
DDRD
PORTD
DDRE
PORTE
PIR1
PIE1
TMR1
TMR2
TMR3L
TMR3H
PR1
PR2
PR3L/CA1L
PR3H/CA1H
PW1DCL
PW2DCL
PW1DCH
PW2DCH
CA2L
CA2H
TCON1
TCON2
PIR2
PIE2
â
RCSTA2
RCREG2
TXSTA2
TXREG2
SPBRG2
18h PRODL
19h PRODH
1Ah General
Purpose
1Fh
RAM
Bank 0 (2) Bank 1 (2) Bank 2 (2, 3) Bank 3 (2, 3)
20h
Bank 5 (1)
DDRF
PORTF
DDRG
PORTG
ADCON0
ADCON1
ADRESL
ADRESH
Bank 6 (1)
SSPADD
SSPCON1
SSPCON2
SSPSTAT
SSPBUF
â
â
â
Bank 7 (1)
PW3DCL
PW3DCH
CA3L
CA3H
CA4L
CA4H
TCON3
â
General
Purpose
RAM
General
Purpose
RAM
General
Purpose
RAM
General
Purpose
RAM
FFh
Note 1: SFR ï¬le locations 10h - 17h are banked. The lower nibble of the BSR speciï¬es the bank. All
unbanked SFRs ignore the Bank Select Register (BSR) bits.
2: General Purpose Registers (GPR) locations 20h - FFh, 120h - 1FFh, 220h - 2FFh, and 320h - 3FFh
are banked. The upper nibble of the BSR speciï¬es this bank. All other GPRs ignore the Bank Select
Register (BSR) bits.
3: These RAM banks are not implemented on the PIC17C752. Reading any register in this bank reads
â0âs.
© 1997 Microchip Technology Inc.
Preliminary
DS30264A-page 273
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