PIC16F1847_13 Datasheet, PDF (96/440 Pages) Microchip Technology – 18/20/28-Pin Flash Microcontrollers with XLP Technology

PIC16(L)F1847
REGISTER 8-9: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4
U-0
—
bit 7
U-0
U-0
U-0
U-0
U-0
R/W/HS-0/0 R/W/HS-0/0
—
—
—
—
—
BCL2IF
SSP2IF
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Bit is set by hardware
bit 7-2
bit 1
bit 0
Unimplemented: Read as ‘0’
BCL2IF: MSSP2 Bus Collision Interrupt Flag bit
1 = A Bus Collision was detected (must be cleared in software)
0 = No Bus collision was detected
SSP2IF: Master Synchronous Serial Port 2 (MSSP2) Interrupt Flag bit
1 = The Transmission/Reception/Bus Condition is complete (must be cleared in software)
0 = Waiting to Transmit/Receive/Bus Condition in progress
Note 1: Interrupt flag bits are set when an inter-
rupt condition occurs, regardless of the
state of its corresponding enable bit or
the Global Enable bit, GIE of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
INTCON
GIE
PEIE TMR0IE INTE
IOCE
TMR0IF
INTF
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA
PS<2:0>
PIE1
TMR1GIE ADIE
RCIE
TXIE
SSP1IE CCP1IE TMR2IE
PIE2
OSFIE
C2IE
C1IE
EEIE
BCL1IE
—
—
PIE3
—
—
CCP4IE CCP3IE TMR6IE
—
TMR4IE
PIE4
—
—
—
—
—
—
BCL2IE
PIR1
TMR1GIF ADIF
RCIF
TXIF
SSP1IF CCP1IF TMR2IF
PIR2
OSFIF
C2IF
C1IF
EEIF
BCL1IF
—
—
PIR3
—
—
CCP4IF CCP3IF TMR6IF
—
TMR4IF
PIR4
—
—
—
—
—
—
BCL2IF
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by interrupts.
Bit 0
IOCF
TMR1IE
CCP2IE
—
SSP2IE
TMR1IF
CCP2IF
—
SSP2IF
Register
on Page
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DS40001453D-page 96
Preliminary
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