PIC16F1847_13 Datasheet, PDF (285/440 Pages) Microchip Technology – 18/20/28-Pin Flash Microcontrollers with XLP Technology

PIC16(L)F1847
REGISTER 25-4: SSPxCON3: SSPx CONTROL REGISTER 3
R-0/0
ACKTIM
bit 7
R/W-0/0
PCIE
R/W-0/0
SCIE
R/W-0/0
BOEN
R/W-0/0
SDAHT
R/W-0/0
SBCDE
R/W-0/0
AHEN
R/W-0/0
DHEN
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
ACKTIM: Acknowledge Time Status bit (I²C mode only)⁽³⁾
1 = Indicates the I²C bus is in an Acknowledge sequence, set on 8^TH falling edge of SCLx clock
0 = Not an Acknowledge sequence, cleared on 9^TH rising edge of SCLx clock
bit 6
PCIE: Stop Condition Interrupt Enable bit (I²C mode only)
1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled⁽²⁾
bit 5
SCIE: Start Condition Interrupt Enable bit (I²C mode only)
1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled⁽²⁾
bit 4
BOEN: Buffer Overwrite Enable bit
In SPI Slave mode:⁽¹⁾
1 = SSPxBUF updates every time that a new data byte is shifted in ignoring the BF bit
0 = If new byte is received with BF bit of the SSPxSTAT register already set, SSPOV bit of the
SSPxCON1 register is set, and the buffer is not updated
In I²C Master mode and SPI Master mode:
This bit is ignored.
In I²C Slave mode:
1 = SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the
state of the SSPOV bit only if the BF bit = 0.
0 = SSPxBUF is only updated when SSPOV is clear
bit 3
SDAHT: SDAx Hold Time Selection bit (I²C mode only)
1 = Minimum of 300 ns hold time on SDAx after the falling edge of SCLx
0 = Minimum of 100 ns hold time on SDAx after the falling edge of SCLx
bit 2
SBCDE: Slave Mode Bus Collision Detect Enable bit (I²C Slave mode only)
If on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the
BCLxIF bit of the PIR2 register is set, and bus goes idle
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
bit 1
AHEN: Address Hold Enable bit (I²C Slave mode only)
1 = Following the 8th falling edge of SCLx for a matching received address byte; CKP bit of the
SSPxCON1 register will be cleared and the SCLx will be held low.
0 = Address holding is disabled
bit 0
DHEN: Data Hold Enable bit (I²C Slave mode only)
1 = Following the 8th falling edge of SCLx for a received data byte; slave hardware clears the CKP bit
of the SSPxCON1 register and SCLx is held low.
0 = Data holding is disabled
Note 1:
2:
3:
For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF.
This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.
 2011-2013 Microchip Technology Inc.
Preliminary
DS40001453D-page 285