PIC16F1847_13 Datasheet, PDF (205/440 Pages) Microchip Technology – 18/20/28-Pin Flash Microcontrollers with XLP Technology

24.1.5 CAPTURE DURING SLEEP
Capture mode depends upon the Timer1 module for
proper operation. There are two options for driving the
Timer1 module in Capture mode. It can be driven by the
instruction clock (FOSC/4), or by an external clock source.
When Timer1 is clocked by FOSC/4, Timer1 will not
increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
Capture mode will operate during Sleep when Timer1
is clocked by an external clock source.
PIC16(L)F1847
24.1.6 ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the Alternate Pin
Function registers, APFCON0 and APFCON1. To
determine which pins can be moved and what their
default locations are upon a Reset, see Section 12.1
“Alternate Pin Function” for more information.
TABLE 24-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
APFCON0 RXDTSEL SDO1SEL SS1SEL P2BSEL CCP2SEL P1DSEL P1CSEL CCP1SEL
CCP1CON
P1M<1:0>
DC1B<1:0>
CCP1M<3:0>
CCPR1L Capture/Compare/PWM Register Low Byte (LSB)
CCPR1H Capture/Compare/PWM Register High Byte (MSB)
CM1CON0 C1ON
C1OUT
C1OE
C1POL
—
C1SP
C1HYS C1SYNC
CM1CON1 C1INTP C1INTN
C1PCH<1:0>
—
—
C1NCH<1:0>
CM2CON0 C2ON
C2OUT
C2OE
C2POL
—
C2SP
C2HYS C2SYNC
CM2CON1 C2INTP C2INTN
C2PCH<1:0>
—
—
C2NCH<1:0>
CCP2CON
P2M<1:0>
DC2B<1:0>
CCP2M<3:0>
CCPR2L Capture/Compare/PWM Register Low Byte (LSB)
CCPR2H Capture/Compare/PWM Register High Byte (MSB)
CCP3CON
—
—
DC3B<1:0>
CCP3M<3:0>
CCPR3L Capture/Compare/PWM Register Low Byte (LSB)
CCPR3H Capture/Compare/PWM Register High Byte (MSB)
CCP4CON
—
—
DC4B<1:0>
CCP4M<3:0)>
CCPR4L Capture/Compare/PWM Register Low Byte (LSB)
CCPR4H Capture/Compare/PWM Register High Byte (MSB)
INTCON
GIE
PEIE
TMR0IE
INTE
IOCE
TMR0IF
INTF
IOCF
PIE1
TMR1GIE ADIE
RCIE
TXIE
SSP1IE
CCP1IE TMR2IE TMR1IE
PIE2
OSFIE
C2IE
C1IE
EEIE
BCL1IE
—
—
CCP2IE
PIE3
—
—
CCP4IE CCP3IE
TMR6IE
—
TMR4IE
—
PIR1
TMR1GIF ADIF
RCIF
TXIF
SSP1IF
CCP1IF TMR2IF TMR1IF
PIR2
OSFIF
C2IF
C1IF
EEIF
BCL1IF
—
—
CCP2IF
PIR3
—
—
CCP4IF CCP3IF
TMR6IF
—
TMR4IF
—
T1CON
TMR1CS<1:0>
T1CKPS<1:0>
T1OSCEN T1SYNC
—
TMR1ON
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL
T1GSS<1:0>
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TRISA
TRISA7 TRISA6 TRISA5 TRISA4
TRISA3
TRISA2 TRISA1 TRISA0
TRISB
TRISB7 TRISB6 TRISB5 TRISB4
TRISB3
TRISB2 TRISB1 TRISB0
Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by Capture mode.
* Page provides register information.
Register
on Page
118
226
204*
204*
170
171
171
171
226
226
226
226
226
226
226
226
226
88
89
90
91
93
94
95
185
186
177*
177*
120
126
 2011-2013 Microchip Technology Inc.
Preliminary
DS40001453D-page 205