PIC16F1847_13 Datasheet, PDF (175/440 Pages) Microchip Technology – 18/20/28-Pin Flash Microcontrollers with XLP Technology

PIC16(L)F1847
REGISTER 20-1: OPTION_REG: OPTION REGISTER
R/W-1/1
WPUEN
bit 7
R/W-1/1
INTEDG
R/W-1/1
TMR0CS
R/W-1/1
TMR0SE
R/W-1/1
PSA
R/W-1/1
R/W-1/1
PS<2:0>
R/W-1/1
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
WPUEN: Weak Pull-up Enable bit
1 = All weak pull-ups are disabled (except MCLR, if it is enabled)
0 = Weak pull-ups are enabled by individual WPUx latch values
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
TMR0CS: Timer0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
TMR0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is not used by the Timer0 module (1:1 Rate)
0 = Prescaler is used by the Timer0 module
PS<2:0>: Prescaler Rate Select bits
Bit Value Timer0 Rate
000
1:2
001
1:4
010
1:8
011
1 : 16
100
1 : 32
101
1 : 64
110
1 : 128
111
1 : 256
TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPSCON0 CPSON CPSRM —
—
CPSRNG<1:0> CPSOUT T0XCS
INTCON
GIE
PEIE TMR0IE INTE
IOCE TMR0IF INTF
IOCF
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA
PS<2:0>
TMR0
Timer0 Module Register
TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module.
* Page provides register information.
Register
on Page
323
88
175
173*
120
 2011-2013 Microchip Technology Inc.
Preliminary
DS40001453D-page 175