PIC16F1847_13 Datasheet, PDF (373/440 Pages) Microchip Technology – 18/20/28-Pin Flash Microcontrollers with XLP Technology

PIC16(L)F1847
FIGURE 30-21:
SCLx
SDAx
In
SDAx
Out
I²C™ BUS DATA TIMING
SP103 ^SP100
SP101
SP90
SP91
SP106
SP107
SP109
SP109
SP102
SP92
SP110
Note: Refer to Figure 30-5 for load conditions.
TABLE 30-16: I²C™ BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min.
Max. Units
Conditions
SP100*
SP101*
SP102*
SP103*
SP106*
SP107*
SP109*
SP110*
SP111
*
Note 1:
2:
THIGH
Clock high time
100 kHz mode
4.0
—
s Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
s Device must operate at a
minimum of 10 MHz
SSP module
1.5TCY
—
—
TLOW
Clock low time
100 kHz mode
4.7
—
s Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
s Device must operate at a
minimum of 10 MHz
SSP module
1.5TCY
—
—
TR
SDA and SCL
100 kHz mode
—
1000 ns
rise time
400 kHz mode
20 + 0.1CB 300
ns CB is specified to be from
10-400 pF
TF
SDA and SCL fall time 100 kHz mode
—
250
ns
400 kHz mode
20 + 0.1CB 250
ns CB is specified to be from
10-400 pF
THD:DAT Data input hold time 100 kHz mode
0
—
ns
400 kHz mode
0
0.9
s
TSU:DAT Data input setup time 100 kHz mode
250
—
ns (Note 2)
400 kHz mode
100
—
ns
TAA
Output valid from
100 kHz mode
clock
400 kHz mode
—
3500 ns (Note 1)
—
—
ns
TBUF
Bus free time
100 kHz mode
400 kHz mode
4.7
—
s Time the bus must be free
1.3
—
s ^{before a new transmission}
can start
CB
Bus capacitive loading
—
400 pF
These parameters are characterized but not tested.
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A Fast mode (400 kHz) I²C™ bus device can be used in a Standard mode (100 kHz) I²C bus system, but the require-
ment TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low
period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit
to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I²C bus specification),
before the SCL line is released.
 2011-2013 Microchip Technology Inc.
Preliminary
DS40001453D-page 373