PIC16F1847_13 Datasheet, PDF (93/440 Pages) Microchip Technology – 18/20/28-Pin Flash Microcontrollers with XLP Technology

PIC16(L)F1847
REGISTER 8-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0/0
TMR1GIF
bit 7
R/W-0/0
ADIF
R-0/0
RCIF
R-0/0
TXIF
R/W-0/0
SSP1IF
R/W-0/0
CCP1IF
R/W-0/0
TMR2IF
R/W-0/0
TMR1IF
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
TMR1GIF: Timer1 Gate Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 6
ADIF: ADC Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 5
RCIF: USART Receive Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4
TXIF: USART Transmit Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 3
SSP1IF: Synchronous Serial Port 1 (MSSP1) Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 2
CCP1IF: CCP1 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 1
TMR2IF: Timer2 to PR2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 0
TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
 2011-2013 Microchip Technology Inc.
Preliminary
DS40001453D-page 93