PIC16F1847_13 Datasheet, PDF(31/440 Page) Microchip Technology – 18/20/28-Pin Flash Microcontrollers with XLP Technology

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PIC16F1847_13 Datasheet, PDF (31/440 Pages) Microchip Technology – 18/20/28-Pin Flash Microcontrollers with XLP Technology

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PIC16(L)F1847

TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bank 4

200h(1) INDF0

201h(1) INDF1

202h(1)

203h(1)

204h(1)

205h(1)

206h(1)

207h(1)

208h(1)

209h(1)

20Ah(1)

20Bh(1)

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

Program Counter (PC) Least Significant Byte

â

â

â

TO

PD

Z

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

â

â

â

BSR<4:0>

Working Register

â

Write Buffer for the upper 7 bits of the Program Counter

GIE

PEIE

TMR0IE

INTE

IOCE

TMR0IF

DC

INTF

20Ch WPUA

â

â

WPUA5

â

â

â

â

20Dh WPUB

WPUB7

WPUB6

WPUB5

WPUB4 WPUB3 WPUB2 WPUB1

20Eh â

Unimplemented

20Fh

â

Unimplemented

210h

â

Unimplemented

211h

212h

213h

SSP1BUF

SSP1ADD

SSP1MSK

Synchronous Serial Port Receive Buffer/Transmit Register

Synchronous Serial Port (I2C mode) Address Register

Synchronous Serial Port (I2C mode) Address Mask Register

214h

SSP1STAT

SMP

CKE

D/A

P

S

R/W

UA

215h

SSP1CON1

WCOL

SSPOV

SSPEN

CKP

SSPM3 SSPM2 SSPM1

216h

SSP1CON2

GCEN ACKSTAT ACKDT

ACKEN

RCEN

PEN

RSEN

217h

SSP1CON3 ACKTIM

PCIE

SCIE

BOEN

SDAHT SBCDE AHEN

218h

â

Unimplemented

219h

21Ah

21Bh

SSP2BUF

SSP2ADD

SSP2MSK

Synchronous Serial Port Receive Buffer/Transmit Register

Synchronous Serial Port (I2C mode) Address Register

Synchronous Serial Port (I2C mode) Address Mask Register

21Ch SSP2STAT

SMP

CKE

D/A

P

S

R/W

UA

21Dh SSP2CON1

WCOL

SSPOV

SSPEN

CKP

SSPM3 SSPM2 SSPM1

21Eh SSP2CON2

GCEN ACKSTAT ACKDT

ACKEN

RCEN

PEN

RSEN

21Fh

SSP2CON3

ACKTIM

PCIE

SCIE

BOEN

SDAHT SBCDE AHEN

Legend:

Note 1:

2:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.

Shaded locations are unimplemented, read as â0â.

These registers can be addressed from any bank.

Unimplemented, read as â1â.

Bit 0

Value on

POR, BOR

Value on

all other

Resets

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

0000 0000 0000 0000

C

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

IOCF

â

WPUB0

-000 0000 -000 0000

0000 000x 0000 000u

--1- ---- --1- ----

1111 1111 1111 1111

â

â

â

â

â

â

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

BF

SSPM0

SEN

DHEN

1111 1111 1111 1111

0000 0000 0000 0000

0000 0000 0000 0000

0000 0000 0000 0000

0000 0000 0000 0000

â

â

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

BF

SSPM0

SEN

DHEN

1111 1111 1111 1111

0000 0000 0000 0000

0000 0000 0000 0000

0000 0000 0000 0000

0000 0000 0000 0000

ï£ 2011-2013 Microchip Technology Inc.

Preliminary

DS40001453D-page 31

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