PIC16F1847_13 Datasheet, PDF (314/440 Pages) Microchip Technology – 18/20/28-Pin Flash Microcontrollers with XLP Technology

PIC16(L)F1847
26.4.2.3 EUSART Synchronous Slave
Reception
The operation of the Synchronous Master and Slave
modes is identical (Section 26.4.1.5 “Synchronous
Master Reception”), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
never Idle
• SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
26.4.2.4 Synchronous Slave Reception
Setup:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
2. Clear the ANSEL bit for both the CK and DT pins
(if applicable).
3. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
4. If 9-bit reception is desired, set the RX9 bit.
5. Set the CREN bit to enable reception.
6. The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
7. If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
8. Retrieve the eight Least Significant bits from the
receive FIFO by reading the RCREG register.
9. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
TABLE 26-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
APFCON0
APFCON1
BAUDCON
RXDTSEL
—
ABDOVF
SDO1SEL
—
RCIDL
SS1SEL
—
—
P2BSEL
—
SCKP
CCP2SEL
—
BRG16
P1DSEL
—
—
P1CSEL
—
WUE
CCP1SEL
TXCKSEL
ABDEN
INTCON
GIE
PEIE
TMR0IE
INTE
IOCE
TMR0IF
INTF
IOCF
PIE1
TMR1GIE ADIE
RCIE
TXIE
SSP1IE CCP1IE TMR2IE TMR1IE
PIR1
TMR1GIF ADIF
RCIF
TXIF
SSP1IF CCP1IF TMR2IF TMR1IF
RCREG
EUSART Receive Data Register
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
TRISB
TXSTA
TRISB7
CSRC
TRISB6
TX9
TRISB5
TXEN
TRISB4
SYNC
TRISB3
SENDB
TRISB2
BRGH
TRISB1
TRMT
TRISB0
TX9D
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.
* Page provides register information.
Register
on Page
118
118
298
88
89
93
292*
297
126
296
DS40001453D-page 314
Preliminary
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