PIC16F1847_13 Datasheet, PDF (30/440 Pages) Microchip Technology – 18/20/28-Pin Flash Microcontrollers with XLP Technology

PIC16(L)F1847
TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bank 3
180h⁽¹⁾ INDF0
181h⁽¹⁾ INDF1
182h⁽¹⁾
183h⁽¹⁾
184h⁽¹⁾
185h⁽¹⁾
186h⁽¹⁾
187h⁽¹⁾
188h⁽¹⁾
189h⁽¹⁾
18Ah⁽¹⁾
18Bh⁽¹⁾
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
—
—
—
TO
PD
Z
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR<4:0>
Working Register
—
Write Buffer for the upper 7 bits of the Program Counter
GIE
PEIE
TMR0IE
INTE
IOCE
TMR0IF
DC
INTF
18Ch ANSELA
—
—
—
ANSA4
ANSA3 ANSA2 ANSA1
18Dh ANSELB
ANSB7
ANSB6
ANSB5
ANSB4
ANSB3 ANSB2 ANSB1
18Eh
—
Unimplemented
18Fh
—
Unimplemented
190h
—
Unimplemented
191h
192h
EEADRL
EEADRH
EEPROM / Program Memory Address Register Low Byte
—⁽²⁾ EEPROM / Program Memory Address Register High Byte
193h
EEDATL
EEPROM / Program Memory Read Data Register Low Byte
194h
EEDATH
—
—
EEPROM / Program Memory Read Data Register High Byte
195h
EECON1
EEPGD
CFGS
LWLO
FREE
WRERR WREN
WR
196h
EECON2
EEPROM control register 2
197h
—
Unimplemented
198h
—
Unimplemented
199h
RCREG
USART Receive Data Register
19Ah
TXREG
USART Transmit Data Register
19Bh
SPBRGL
Baud Rate Generator Data Register Low
19Ch
SPBRGH
Baud Rate Generator Data Register High
19Dh RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
19Eh
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
19Fh
BAUDCON
ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
Legend:
Note 1:
2:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
Unimplemented, read as ‘1’.
Bit 0
Value on
POR, BOR
Value on
all other
Resets
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
0000 0000 0000 0000
C
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
IOCF
ANSA0
—
-000 0000 -000 0000
0000 000x 0000 000u
---1 1111 ---1 1111
1111 111- 1111 111-
—
—
—
—
—
—
0000 0000 0000 0000
1000 0000 1000 0000
xxxx xxxx uuuu uuuu
--xx xxxx --uu uuuu
RD 0000 x000 0000 q000
0000 0000 0000 0000
—
—
—
—
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
RX9D
TX9D
ABDEN
0000 0000 0000 0000
0000 000x 0000 000x
0000 0010 0000 0010
01-0 0-00 01-0 0-00
DS40001453D-page 30
Preliminary
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