PIC16F1847_13 Datasheet, PDF (41/440 Pages) Microchip Technology – 18/20/28-Pin Flash Microcontrollers with XLP Technology

FIGURE 3-7:
ACCESSING THE STACK EXAMPLE 4
PIC16(L)F1847
TOSH:TOSL
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
When the stack is full, the next CALL or
interrupt will set the Stack Pointer to
0x10. This is identical to address 0x00
so the stack will wrap and overwrite the
return address at 0x00. If the Stack
Overflow/Underflow Reset is enabled, a
Reset will occur and location 0x00 will
not be overwritten.
STKPTR = 0x10
3.5.2 OVERFLOW/UNDERFLOW RESET
If the STVREN bit in Configuration Words is set to ‘1’,
the device will be reset if the stack is PUSHed beyond
the sixteenth level or POPed beyond the first level,
setting the appropriate bits (STKOVF or STKUNF,
respectively) in the PCON register.
3.6 Indirect Addressing
The INDFn registers are not physical registers. Any
instruction that accesses an INDFn register actually
accesses the register at the address specified by the
File Select Registers (FSR). If the FSRn address
specifies one of the two INDFn registers, the read will
return ‘0’ and the write will not occur (though Status bits
may be affected). The FSRn register value is created
by the pair FSRnH and FSRnL.
The FSR registers form a 16-bit address that allows an
addressing space with 65536 locations. These locations
are divided into three memory regions:
• Traditional Data Memory
• Linear Data Memory
• Program Flash Memory
 2011-2013 Microchip Technology Inc.
Preliminary
DS40001453D-page 41