PIC16F1847_13 Datasheet, PDF (139/440 Pages) Microchip Technology – 18/20/28-Pin Flash Microcontrollers with XLP Technology

PIC16(L)F1847
TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD)
Device Frequency (FOSC)
ADC
Clock Source
ADCS<2:0>
32 MHz
20 MHz
16 MHz
8 MHz
4 MHz
1 MHz
Fosc/2
Fosc/4
Fosc/8
Fosc/16
Fosc/32
Fosc/64
FRC
000
62.5ns⁽²⁾
100 ns⁽²⁾
125 ns⁽²⁾
250 ns⁽²⁾
500 ns⁽²⁾
2.0 s
100
125 ns⁽²⁾
200 ns⁽²⁾
250 ns⁽²⁾
500 ns⁽²⁾
1.0 s
4.0 s
001
0.5 s⁽²⁾
400 ns⁽²⁾
0.5 s⁽²⁾
1.0 s
2.0 s
8.0 s⁽³⁾
101
800 ns
800 ns
1.0 s
2.0 s
4.0 s
16.0 s⁽³⁾
010
1.0 s
1.6 s
2.0 s
4.0 s
8.0 s⁽³⁾
32.0 s⁽³⁾
110
2.0 s
3.2 s
4.0 s
8.0 s⁽³⁾
16.0 s⁽³⁾
64.0 s⁽³⁾
x11
1.0-6.0 s^(1,4) 1.0-6.0 s^(1,4) 1.0-6.0 s^(1,4) 1.0-6.0 s^(1,4) 1.0-6.0 s^(1,4) 1.0-6.0 s^(1,4)
Legend:
Note 1:
2:
3:
4:
Shaded cells are outside of recommended range.
The FRC source has a typical TAD time of 1.6 s for VDD.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the
system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the
device in Sleep mode.
FIGURE 16-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
 2011-2013 Microchip Technology Inc.
Preliminary
DS40001453D-page 139