PIC16F1847_13 Datasheet, PDF (32/440 Pages) Microchip Technology – 18/20/28-Pin Flash Microcontrollers with XLP Technology

PIC16(L)F1847
TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
Bank 5
280h⁽¹⁾ INDF0
281h⁽¹⁾ INDF1
282h⁽¹⁾
283h⁽¹⁾
284h⁽¹⁾
285h⁽¹⁾
286h⁽¹⁾
287h⁽¹⁾
288h⁽¹⁾
289h⁽¹⁾
28Ah⁽¹⁾
28Bh⁽¹⁾
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
—
—
—
TO
PD
Z
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR<4:0>
Working Register
—
Write Buffer for the upper 7 bits of the Program Counter
GIE
PEIE
TMR0IE
INTE
IOCE
TMR0IF
DC
INTF
C
IOCF
28Ch —
Unimplemented
28Dh —
Unimplemented
28Eh
—
Unimplemented
28Fh
—
Unimplemented
290h
—
Unimplemented
291h
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
292h
CCPR1H
Capture/Compare/PWM Register 1 (MSB)
293h
CCP1CON
P1M<1:0>
DC1B<1:0>
CCP1M<3:0>
294h
PWM1CON P1RSEN
P1DC<6:0>
295h
CCP1AS
CCP1ASE
CCP1AS<2:0>
PSS1AC<1:0>
PSS1BD<1:0>
296h
PSTR1CON
—
—
—
STR1SYNC STR1D STR1C STR1B STR1A
297h
—
Unimplemented
298h
CCPR2L
Capture/Compare/PWM Register 2 (LSB)
299h
CCPR2H
Capture/Compare/PWM Register 2 (MSB)
29Ah
CCP2CON
P2M<1:0>
DC2B<1:0>
CCP2M<3:0>
29Bh
PWM2CON
P2RSEN
P2DC<6:0>
29Ch CCP2AS
CCP2ASE
CCP2AS<2:0>
PSS2AC<1:0>
PSS2BD<1:0>
29Dh PSTR2CON
—
—
—
STR2SYNC STR2D STR2C STR2B STR2A
29Eh
CCPTMRS
C4TSEL<1:0>
C3TSEL<1:0>
C2TSEL<1:0>
C1TSEL<1:0>
29Fh
—
Unimplemented
Legend:
Note 1:
2:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
Unimplemented, read as ‘1’.
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
—
—
—
—
—
—
—
—
—
—
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
---0 0001 ---0 0001
—
—
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
---0 0001 ---0 0001
0000 0000 0000 0000
—
—
DS40001453D-page 32
Preliminary
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