PIC16F1847_13 Datasheet, PDF (266/440 Pages) Microchip Technology – 18/20/28-Pin Flash Microcontrollers with XLP Technology

PIC16(L)F1847
25.6.5
I²C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated Start condition (Figure 25-27) occurs when
the RSEN bit of the SSPxCON2 register is
programmed high and the Master state machine is no
longer active. When the RSEN bit is set, the SCLx pin
is asserted low. When the SCLx pin is sampled low, the
Baud Rate Generator is loaded and begins counting.
The SDAx pin is released (brought high) for one Baud
Rate Generator count (TBRG). When the Baud Rate
Generator times out, if SDAx is sampled high, the SCLx
pin will be deasserted (brought high). When SCLx is
sampled high, the Baud Rate Generator is reloaded
and begins counting. SDAx and SCLx must be sam-
pled high for one TBRG. This action is then followed by
assertion of the SDAx pin (SDAx = 0) for one TBRG
while SCLx is high. SCLx is asserted low. Following
this, the RSEN bit of the SSPxCON2 register will be
automatically cleared and the Baud Rate Generator will
not be reloaded, leaving the SDAx pin held low. As
soon as a Start condition is detected on the SDAx and
SCLx pins, the S bit of the SSPxSTAT register will be
set. The SSPxIF bit will not be set until the Baud Rate
Generator has timed out.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDAx is sampled low when SCLx
goes from low-to-high.
• SCLx goes low before SDAx is
asserted low. This may indicate
that another master is attempting to
transmit a data ‘1’.
FIGURE 25-27: REPEAT START CONDITION WAVEFORM
SDAx
Write to SSPxCON2
occurs here
SDAx = 1,
SCLx (no change)
SDAx = 1,
SCLx = 1
S bit set by hardware
At completion of Start bit,
hardware clears RSEN bit
and sets SSPxIF
TBRG TBRG TBRG
1st bit
SCLx
Write to SSPxBUF occurs here
TBRG
Sr
Repeated Start
TBRG
DS40001453D-page 266
Preliminary
 2011-2013 Microchip Technology Inc.