PIC16F1847_13 Datasheet, PDF (193/440 Pages) Microchip Technology – 18/20/28-Pin Flash Microcontrollers with XLP Technology

PIC16(L)F1847
23.0 DATA SIGNAL MODULATOR
The Data Signal Modulator (DSM) is a peripheral which
allows the user to mix a data stream, also known as a
modulator signal, with a carrier signal to produce a
modulated output.
Both the carrier and the modulator signals are supplied
to the DSM module either internally, from the output of
a peripheral, or externally through an input pin.
The modulated output signal is generated by perform-
ing a logical “AND” operation of both the carrier and
modulator signals and then provided to the MDOUT pin.
The carrier signal is comprised of two distinct and
separate signals. A carrier high (CARH) signal and a
carrier low (CARL) signal. During the time in which the
modulator (MOD) signal is in a logic high state, the
DSM mixes the carrier high signal with the modulator
signal. When the modulator signal is in a logic low
state, the DSM mixes the carrier low signal with the
modulator signal.
Using this method, the DSM can generate the following
types of Key Modulation schemes:
• Frequency-Shift Keying (FSK)
• Phase-Shift Keying (PSK)
• On-Off Keying (OOK)
Additionally, the following features are provided within
the DSM module:
• Carrier Synchronization
• Carrier Source Polarity Select
• Carrier Source Pin Disable
• Programmable Modulator Data
• Modulator Source Pin Disable
• Modulated Output Polarity Select
• Slew Rate Control
Figure 23-1 shows a Simplified Block Diagram of the
Data Signal Modulator peripheral.
FIGURE 23-1:
SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR
MDCH<3:0>
VSS
MDCIN1
MDCIN2
CLKR
CCP1
CCP2
CCP3
CCP4
Reserved
No Channel
Selected
0000
0001
0010
0011
0100
0101 CARH
0110
0111
1000
*
*
1111
MDMS<3:0>
MDBIT
MDMIN
CCP1
CCP2
CCP3
CCP4
Comparator C1
Comparator C2
MSSP1 SDO1
MSSP2 SDO2
TX
Reserved
No Channel
Selected
0000
0001
0010
0011
0100
0101
0110 _MOD
0111
1000
1001
1010
1011
*
*
1111
MDEN
EN
MDCHPOL
Data Signal
Modulator
D
SYNC
Q
1
0
MDCHSYNC
MDOPOL ^MDOE
MDOUT
MDCL<3:0>
VSS
MDCIN1
MDCIN2
CLKR
CCP1
CCP2
CCP3
CCP4
Reserved
No Channel
Selected
0000
0001
0010
0011
0100
0101 CARL
0110
0111
1000
*
*
1111
MDCLPOL
D
SYNC
Q
1
0
MDCLSYNC
 2011-2013 Microchip Technology Inc.
Preliminary
DS40001453D-page 193