PIC16F1847_13 Datasheet, PDF (70/440 Pages) Microchip Technology – 18/20/28-Pin Flash Microcontrollers with XLP Technology

PIC16(L)F1847
6.5 Register Definitions: Reference Clock Control
REGISTER 6-1: CLKRCON: REFERENCE CLOCK CONTROL REGISTER
R/W-0/0
CLKREN
bit 7
R/W-0/0
CLKROE
R/W-1/1
CLKRSLR
R/W-1/1
R/W-0/0
CLKRDC<1:0>
R/W-0/0
R/W-0/0
CLKRDIV<2:0>
R/W-0/0
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5
bit 4-3
bit 2-0
CLKREN: Reference Clock Module Enable bit
1 = Reference clock module is enabled
0 = Reference clock module is disabled
CLKROE: Reference Clock Output Enable bit⁽³⁾
1 = Reference Clock output is enabled on CLKR pin
0 = Reference Clock output disabled on CLKR pin
CLKRSLR: Reference Clock Slew Rate Control Limiting Enable bit
1 = Slew Rate limiting is enabled
0 = Slew Rate limiting is disabled
CLKRDC<1:0>: Reference Clock Duty Cycle bits
11 = Clock outputs duty cycle of 75%
10 = Clock outputs duty cycle of 50%
01 = Clock outputs duty cycle of 25%
00 = Clock outputs duty cycle of 0%
CLKRDIV<2:0> Reference Clock Divider bits
111 = Base clock value divided by 128
110 = Base clock value divided by 64
101 = Base clock value divided by 32
100 = Base clock value divided by 16
011 = Base clock value divided by 8
010 = Base clock value divided by 4
001 = Base clock value divided by 2⁽¹⁾
000 = Base clock value⁽²⁾
Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle.
2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0%
is selected.
3: To route CLKR to pin, CLKOUTEN of Configuration Words = 1 is required. CLKOUTEN of Configuration
Words = 0 will result in FOSC/4. See Section 6.3 “Conflicts with the CLKR pin” for details.
DS40001453D-page 70
Preliminary
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