PIC16F1847_13 Datasheet, PDF (291/440 Pages) Microchip Technology – 18/20/28-Pin Flash Microcontrollers with XLP Technology

PIC16(L)F1847
FIGURE 26-4:
Write to TXREG
BRG Output
(Shift Clock)
TX/CK
pin
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Word 1
Word 2
1 TCY
Start bit
Word 1
Transmit Shift Reg.
bit 0
1 TCY
bit 1
Word 1
bit 7/8 _{Stop bit}
Start bit
bit 0
Word 2
Word 2
Transmit Shift Reg.
Note:
This timing diagram shows two consecutive transmissions.
TABLE 26-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
APFCON0
RXDTSEL SDO1SEL SS1SEL P2BSEL CCP2SEL P1DSEL P1CSEL
APFCON1
—
—
—
—
—
—
—
BAUDCON
ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
INTCON
GIE
PEIE
TMR0IE
INTE
IOCE
TMR0IF
INTF
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
SPBRGL
BRG<7:0>
SPBRGH
BRG<15:8>
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TXREG
EUSART Transmit Data Register
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Asynchronous Transmission.
* Page provides register information.
Bit 0
CCP1SEL
TXCKSEL
ABDEN
IOCF
TMR1IE
TMR1IF
RX9D
TRISB0
TX9D
Register on
Page
118
118
298
88
89
93
297
299*
299*
126
289*
296
 2011-2013 Microchip Technology Inc.
Preliminary
DS40001453D-page 291