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| PIC17C7XX_13 Datasheet, PDF (47/306 Pages) Microchip Technology – High-Performance 8-bit CMOS EPROM Microcontrollers with 10-bit A/D | |||
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PIC17C7XX
FIGURE 7-5:
PIC17C7XX REGISTER FILE MAP
Addr
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Fh
20h
Unbanked
INDF0
FSR0
PCL
PCLATH
ALUSTA
T0STA
CPUSTA
INTSTA
INDF1
FSR1
WREG
TMR0L
TMR0H
TBLPTRL
TBLPTRH
BSR
Bank 0
PORTA
DDRB
PORTB
RCSTA1
RCREG1
TXSTA1
TXREG1
SPBRG1
Unbanked
PRODL
PRODH
General
Purpose
RAM
Bank 0(2)
Bank 1(1)
DDRC
PORTC
DDRD
PORTD
DDRE
PORTE
PIR1
PIE1
Bank 2(1)
TMR1
TMR2
TMR3L
TMR3H
PR1
PR2
PR3L/CA1L
PR3H/CA1H
Bank 1(2) Bank 2(2)
Bank 3(1)
PW1DCL
PW2DCL
PW1DCH
PW2DCH
CA2L
CA2H
TCON1
TCON2
Bank 3(2,3)
Bank 4(1)
PIR2
PIE2
â
RCSTA2
RCREG2
TXSTA2
TXREG2
SPBRG2
Bank 5(1)
DDRF
PORTF
DDRG
PORTG
ADCON0
ADCON1
ADRESL
ADRESH
Bank 6(1)
SSPADD
SSPCON1
SSPCON2
SSPSTAT
SSPBUF
â
â
â
Bank 7(1)
PW3DCL
PW3DCH
CA3L
CA3H
CA4L
CA4H
TCON3
â
Bank 8(1,4)
DDRH
PORTH
DDRJ
PORTJ
â
â
â
â
General
Purpose
RAM
General
Purpose
RAM
General
Purpose
RAM
General
Purpose
RAM
FFh
Note 1: SFR file locations 10h - 17h are banked. The lower nibble of the BSR specifies the bank. All unbanked
SFRs ignore the Bank Select Register (BSR) bits.
2: General Purpose Registers (GPR) locations 20h - FFh, 120h - 1FFh, 220h - 2FFh, and 320h - 3FFh are
banked. The upper nibble of the BSR specifies this bank. All other GPRs ignore the Bank Select Register
(BSR) bits.
3: RAM bank 3 is not implemented on the PIC17C752 and the PIC17C762. Reading any unimplemented reg-
ister reads â0âs.
4: Bank 8 is only implemented on the PIC17C76X devices.
ï£ 1998-2013 Microchip Technology Inc.
DS30289C-page 47
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