PIC17C7XX_13 Datasheet, PDF (112/306 Pages) Microchip Technology – High-Performance 8-bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
13.2.2 FOUR CAPTURE MODE
This mode is selected by setting bit CA1/PR3. A block
diagram is shown in Figure 13-6. In this mode, TMR3
runs without a period register and increments from
0000h to FFFFh and rolls over to 0000h. The TMR3
interrupt Flag (TMR3IF) is set on this rollover. The
TMR3IF bit must be cleared in software.
Registers PR3H/CA1H and PR3L/CA1L make a 16-bit
capture register (Capture1). It captures events on pin
RB0/CAP1. Capture mode is configured by the
CA1ED1 and CA1ED0 bits. Capture1 Interrupt Flag bit
(CA1IF) is set upon detection of the capture event. The
corresponding interrupt mask bit is CA1IE. The
Capture1 Overflow Status bit is CA1OVF.
All the captures operate in the same manner. Refer to
Section 13.2.1 for the operation of capture.
FIGURE 13-6:
TIMER3 WITH FOUR CAPTURES BLOCK DIAGRAM
FOSC/4
0
RB5/TCLK3
1
TMR3CS
(TCON1<2>)
TMR3ON
(TCON2<2>)
TMR3H
RB0/CAP1
RB1/CAP2
Edge Select,
Prescaler Select
2
CA1ED1, CA1ED0
(TCON1<5:4>)
Edge Select,
Prescaler Select
2
CA2ED1, CA2ED0
(TCON1<7:6>)
Capture1 Enable
Set CA1IF
(PIR1<2>)
PR3H/CA1H
Capture2 Enable
Set CA2IF
(PIR1<3>)
CA2H
PR3L/CA1L
CA2L
RG4/CAP3
Edge Select,
Prescaler Select
2
CA3ED1: CA3ED0
(TCON3<2:1>)
Capture3 Enable
Set CA3IF
(PIR2<2>)
CA3H
CA3L
RE3/CAP4
Edge Select,
Prescaler Select
2
CA4ED1: CA4ED0
(TCON3<4:3>)
Capture4 Enable
Set CA4IF
(PIR2<3>)
CA4H
CA4L
TMR3L
Set TMR3IF
(PIR1<6>)
DS30289C-page 112
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