PIC17C7XX_13 Datasheet, PDF (23/306 Pages) Microchip Technology – High-Performance 8-bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
5.0 RESET
The PIC17CXXX differentiates between various kinds
of RESET:
• Power-on Reset (POR)
• Brown-out Reset
• MCLR Reset
• WDT Reset
Some registers are not affected in any RESET condi-
tion, their status is unknown on POR and unchanged in
any other RESET. Most other registers are forced to a
“RESET state”. The TO and PD bits are set or cleared
differently in different RESET situations, as indicated in
Table 5-3. These bits, in conjunction with the POR and
BOR bits, are used in software to determine the nature
of the RESET. See Table 5-4 for a full description of the
RESET states of all registers.
When the device enters the “RESET state”, the Data
Direction registers (DDR) are forced set, which will
make the I/O hi-impedance inputs. The RESET state of
some peripheral modules may force the I/O to other
operations, such as analog inputs or the system bus.
Note:
While the device is in a RESET state, the
internal phase clock is held in the Q1 state.
Any processor mode that allows external
execution will force the RE0/ALE pin as a
low output and the RE1/OE and RE2/WR
pins as high outputs.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 5-1.
FIGURE 5-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
BOR Brown-out
Module
Reset
WDT
Module
WDT
Time_Out
Reset
VDD Rise
Detect _{Power_On_Reset}
VDD
OST/PWRT
OST
10-bit Ripple Counter
OSC1
PWRT
On-chip
RC OSC†
10-bit Ripple Counter
S
Chip_Reset
R
Q
(Enable the PWRT timer
only during POR or BOR)
(If PWRT is invoked, or a Wake-up from
SLEEP and OSC type is XT or LF)
† This RC oscillator is shared with the WDT when not in a power-up sequence.
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DS30289C-page 23