PIC17C7XX_13 Datasheet, PDF (24/306 Pages) Microchip Technology – High-Performance 8-bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
5.1 Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST) and Brown-out Reset
(BOR)
5.1.1 POWER-ON RESET (POR)
The Power-on Reset circuit holds the device in RESET
until VDD is above the trip point (in the range of 1.4V -
2.3V). The devices produce an internal RESET for both
rising and falling VDD. To take advantage of the POR,
just tie the MCLR/VPP pin directly (or through a resistor)
to VDD. This will eliminate external RC components
usually needed to create Power-on Reset. A minimum
rise time for VDD is required. See Electrical Specifica-
tions for details.
Figure 5-2 and Figure 5-3 show two possible POR
circuits.
FIGURE 5-2:
USING ON-CHIP POR
VDD
VDD
MCLR
PIC17CXXX
FIGURE 5-3:
VDD VDD
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
D
R
C
R1
MCLR
PIC17CXXX
Note 1: An external Power-on Reset circuit is
required only if VDD power-up time is too
slow. The diode D helps discharge the capac-
itor quickly when VDD powers down.
2: R < 40 k is recommended to ensure that the
voltage drop across R does not exceed 0.2V
(max. leakage current spec. on the MCLR/
VPP pin is 5 A). A larger voltage drop will
degrade VIH level on the MCLR/VPP pin.
3: R1 = 100 to 1 k will limit any current flow-
ing into MCLR from external capacitor C in
the event of MCLR/VPP pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
DS30289C-page 24
5.1.2 POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 96 ms time-out
(nominal) on power-up. This occurs from the rising
edge of the internal POR signal if VDD and MCLR are
tied, or after the first rising edge of MCLR (detected
high). The Power-up Timer operates on an internal RC
oscillator. The chip is kept in RESET as long as the
PWRT is active. In most cases, the PWRT delay allows
VDD to rise to an acceptable level.
The power-up time delay will vary from chip to chip and
with VDD and temperature. See DC parameters for
details.
5.1.3
OSCILLATOR START-UP TIMER
(OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (1024TOSC) delay whenever the PWRT
is invoked, or a wake-up from SLEEP event occurs in XT
or LF mode. The PWRT and OST operate in parallel.
The OST counts the oscillator pulses on the OSC1/
CLKIN pin. The counter only starts incrementing after
the amplitude of the signal reaches the oscillator input
thresholds. This delay allows the crystal oscillator or
resonator to stabilize before the device exits RESET.
The length of the time-out is a function of the crystal/
resonator frequency.
Figure 5-4 shows the operation of the OST circuit. In
this figure, the oscillator is of such a low frequency that
although enabled simultaneously, the OST does not
time-out until after the Power-up Timer time-out.
FIGURE 5-4:
OSCILLATOR START-UP
TIME (LOW FREQUENCY)
POR or BOR Trip Point
VDD
MCLR
OSC2
TOSC1
OST TIME_OUT
TOST
PWRT TIME_OUT
INTERNAL RESET
TPWRT
This figure shows in greater detail the timings involved
with the oscillator start-up timer. In this example, the low
frequency crystal start-up time is larger than power-up
time (TPWRT).
TOSC1 = time for the crystal oscillator to react to an oscil-
lation level detectable by the Oscillator Start-up Timer
(OST).
TOST = 1024TOSC.
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